From: Krzysztof Kozlowski <krzk@kernel.org>
To: daire.mcnamara@microchip.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org
Cc: conor.dooley@microchip.com, lpieralisi@kernel.org, kw@linux.com,
robh@kernel.org, bhelgaas@google.com,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
krzk+dt@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v3 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent
Date: Thu, 13 Jun 2024 09:26:01 +0200 [thread overview]
Message-ID: <60b833ce-730f-466e-8d99-3941d85232ce@kernel.org> (raw)
In-Reply-To: <20240612112213.2734748-4-daire.mcnamara@microchip.com>
On 12/06/2024 13:22, daire.mcnamara@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> PolarFire SoC may be configured in a way that requires non-coherent DMA
> handling. On RISC-V, buses are coherent by default & the dma-noncoherent
> property is required to denote buses or devices that are non-coherent.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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prev parent reply other threads:[~2024-06-13 7:26 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-12 11:22 [PATCH v3 0/3] Fix address translations on MPFS PCIe controller daire.mcnamara
2024-06-12 11:22 ` [PATCH v3 1/3] PCI: microchip: Fix outbound address translation tables daire.mcnamara
2024-06-14 13:17 ` Ilpo Järvinen
2024-06-12 11:22 ` [PATCH v3 2/3] PCI: microchip: Fix inbound " daire.mcnamara
2024-06-14 13:29 ` Ilpo Järvinen
2024-06-19 13:48 ` Daire McNamara
2024-06-12 11:22 ` [PATCH v3 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent daire.mcnamara
2024-06-13 7:26 ` Krzysztof Kozlowski [this message]
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