From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
"Conor Dooley" <conor@kernel.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v6 2/7] dt-bindings: soc: starfive: Add StarFive syscon module
Date: Tue, 4 Jul 2023 15:04:38 +0800 [thread overview]
Message-ID: <61120362-6b19-3683-db18-8d703ae278eb@starfivetech.com> (raw)
In-Reply-To: <c2edda13-c674-df56-d1a2-cb47b405b896@linaro.org>
On 2023/7/4 14:30, Krzysztof Kozlowski wrote:
> On 04/07/2023 04:02, Xingyu Wu wrote:
>> From: William Qiu <william.qiu@starfivetech.com>
>>
>> Add documentation to describe StarFive System Controller Registers.
>>
>> Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>
> I don't think there is a point in reviewing bindings which were never
> tested. I hope you agree with me.
>
> The patch just introduces errors. :(
>
Sorry, it was my fault. I tested it but found the example uncompleted.
And I forgot to test it after completing it. Sorry.
Best regards,
Xingyu Wu
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next prev parent reply other threads:[~2023-07-04 7:08 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 2:02 [PATCH v6 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-07-04 2:02 ` [PATCH v6 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-07-04 2:02 ` [PATCH v6 2/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-07-04 3:52 ` Rob Herring
2023-07-04 6:30 ` Krzysztof Kozlowski
2023-07-04 7:04 ` Xingyu Wu [this message]
2023-07-04 2:02 ` [PATCH v6 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-07-04 2:02 ` [PATCH v6 4/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-07-04 2:02 ` [PATCH v6 5/7] clk: starfive: jh7110-sys: Add PLL clocks source from DTS Xingyu Wu
2023-07-04 2:02 ` [PATCH v6 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu
2023-07-04 2:02 ` [PATCH v6 7/7] riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node Xingyu Wu
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