Re: [PATCH v3 3/7] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA

Conor Dooley
2023-02-27T22:47:57Z

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Hey Evan,

On Tue, Feb 21, 2023 at 11:08:54AM -0800, Evan Green wrote:
> We have an implicit set of base behaviors that userspace depends on,
> which are mostly defined in various ISA specifications.
>
> Co-developed-by: Palmer Dabbelt <palmer@rivosinc.com>
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> Signed-off-by: Evan Green <evan@rivosinc.com>
> ---
>
> Changes in v3:
> - Refactored base ISA behavior probe to allow kernel probing as well,
> in prep for vDSO data initialization.
> - Fixed doc warnings in IMA text list, use :c:macro:.
>
> Documentation/riscv/hwprobe.rst | 21 +++++++++++++++++++++
> arch/riscv/include/asm/hwprobe.h | 2 +-
> arch/riscv/include/uapi/asm/hwprobe.h | 5 +++++
> arch/riscv/kernel/sys_riscv.c | 20 ++++++++++++++++++++
> 4 files changed, 47 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
> index 88b015a2026e..9f2da414fbf8 100644
> --- a/Documentation/riscv/hwprobe.rst
> +++ b/Documentation/riscv/hwprobe.rst
> @@ -37,3 +37,24 @@ The following keys are defined:
> defined by the RISC-V privileged architecture specification.
> * :c:macro:`RISCV_HWPROBE_KEY_MIMPLID`: Contains the value of ``mimplid``, as
> defined by the RISC-V privileged architecture specification.
> +* :c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base
> + user-visible behavior that this kernel supports. The following base user ABIs
> + are defined:
> +
> + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or
> + rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the
> + privileged ISA, with the following known exceptions (more exceptions may be
> + added, but only if it can be demonstrated that the user ABI is not broken):
> +
> + * The :fence.i: instruction cannot be directly executed by userspace
> + programs (it may still be executed in userspace via a
> + kernel-controlled mechanism such as the vDSO).
> +* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions
> + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`:
> + base system behavior.
> +
> + * :c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as
> + defined by commit cd20cee ("FMIN/FMAX now implement
> + minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.
> + * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined
> + by version 2.2 of the RISC-V ISA manual.

I think I asked for some newlines, but this all seems kinda random now
as to whether there is a blank line between list items or not.

> diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
> index 02c2f1f7417e..f2b224550923 100644
> --- a/arch/riscv/kernel/sys_riscv.c
> +++ b/arch/riscv/kernel/sys_riscv.c
> @@ -9,6 +9,7 @@
> #include <asm/cacheflush.h>
> #include <asm/hwprobe.h>
> #include <asm/sbi.h>
> +#include <asm/switch_to.h>
> #include <asm/uaccess.h>
> #include <asm/unistd.h>
> #include <asm-generic/mman-common.h>
> @@ -124,6 +125,25 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
> case RISCV_HWPROBE_KEY_MIMPID:
> hwprobe_arch_id(pair, cpus);
> break;
> + /*
> + * The kernel already assumes that the base single-letter ISA
> + * extensions are supported on all harts, and only supports the
> + * IMA base, so just cheat a bit here and tell that to
> + * userspace.
> + */
> + case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
> + pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA;
> + break;
> +
> + case RISCV_HWPROBE_KEY_IMA_EXT_0:
> + pair->value = 0;
> + if (has_fpu())
> + pair->value |= RISCV_HWPROBE_IMA_FD;
> +
> + if (elf_hwcap & RISCV_ISA_EXT_c)
> + pair->value |= RISCV_HWPROBE_IMA_C;
> +
> + break;
>
> /*
> * For forward compatibility, unknown keys don't fail the whole

This looks a lot nicer after the refactor, sans the {}.
With a consistent approach taken to newlines:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

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