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Mon, 09 Sep 2024 04:38:55 -0700 (PDT) Received: from localhost ([37.72.3.43]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378956d3743sm5846883f8f.79.2024.09.09.04.38.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Sep 2024 04:38:55 -0700 (PDT) Message-ID: <66dede4f.5d0a0220.1ef0e1.c922@mx.google.com> X-Google-Original-Message-ID: <87mskhjbue.fsf@> From: =?utf-8?Q?Miquel_Sabat=C3=A9_Sol=C3=A0?= To: Conor Dooley Cc: , , , , , , Subject: Re: [PATCH v2] riscv: hwprobe: export Zicntr and Zihpm extensions In-Reply-To: <20240909-raving-reproach-74431f57896d@wendy> (Conor Dooley's message of "Mon, 9 Sep 2024 12:11:46 +0100") Organization: Linux Private Site References: <20240817075629.262318-1-mikisabate@gmail.com> <20240820044749.557349-1-mikisabate@gmail.com> <66d9605f.5d0a0220.3dabb6.3586@mx.google.com> <20240909-raving-reproach-74431f57896d@wendy> Date: Mon, 09 Sep 2024 13:38:49 +0200 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240909_123900_290082_732C0E6C X-CRM114-Status: GOOD ( 22.80 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============8820962177756087237==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============8820962177756087237== Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha512; protocol="application/pgp-signature" --=-=-= Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On dl., de set. 09 2024, Conor Dooley wrote: > On Thu, Sep 05, 2024 at 09:40:14AM +0200, Miquel Sabat=C3=A9 Sol=C3=A0 wr= ote: >> On dt., d=E2=80=99ag. 20 2024, Miquel Sabat=C3=A9 Sol=C3=A0 wrote: >>=20 >> > Export Zicntr and Zihpm ISA extensions through the hwprobe syscall. >> > >> > Signed-off-by: Miquel Sabat=C3=A9 Sol=C3=A0 >> > --- >> > Documentation/arch/riscv/hwprobe.rst | 6 ++++++ >> > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ >> > arch/riscv/kernel/sys_hwprobe.c | 2 ++ >> > 3 files changed, 10 insertions(+) >> > >> > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch= /riscv/hwprobe.rst >> > index 3db60a0911df..cfd2929d0562 100644 >> > --- a/Documentation/arch/riscv/hwprobe.rst >> > +++ b/Documentation/arch/riscv/hwprobe.rst >> > @@ -183,6 +183,9 @@ The following keys are defined: >> > defined in the Atomic Compare-and-Swap (CAS) instructions manu= al starting >> > from commit 5059e0ca641c ("update to ratified"). >> >=20=20 >> > + * :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version= 2.0 >> > + is supported as defined in the RISC-V ISA manual. >> > + >> > * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supp= orted as >> > defined in the RISC-V Integer Conditional (Zicond) operations = extension >> > manual starting from commit 95cf1f9 ("Add changes requested by= Ved >> > @@ -192,6 +195,9 @@ The following keys are defined: >> > supported as defined in the RISC-V ISA manual starting from co= mmit >> > d8ab5c78c207 ("Zihintpause is ratified"). >> >=20=20 >> > + * :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2= .0 >> > + is supported as defined in the RISC-V ISA manual. >> > + >> > * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve= 32x is >> > supported, as defined by version 1.0 of the RISC-V Vector extensi= on manual. >> >=20=20 >> > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/includ= e/uapi/asm/hwprobe.h >> > index b706c8e47b02..098a815b3fd4 100644 >> > --- a/arch/riscv/include/uapi/asm/hwprobe.h >> > +++ b/arch/riscv/include/uapi/asm/hwprobe.h >> > @@ -72,6 +72,8 @@ struct riscv_hwprobe { >> > #define RISCV_HWPROBE_EXT_ZCF (1ULL << 46) >> > #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) >> > #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) >> > +#define RISCV_HWPROBE_EXT_ZICNTR (1ULL << 49) >> > +#define RISCV_HWPROBE_EXT_ZIHPM (1ULL << 50) >> > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 >> > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) >> > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) >> > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_h= wprobe.c >> > index 8d1b5c35d2a7..910b41b6a7ab 100644 >> > --- a/arch/riscv/kernel/sys_hwprobe.c >> > +++ b/arch/riscv/kernel/sys_hwprobe.c >> > @@ -107,9 +107,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe= *pair, >> > EXT_KEY(ZCB); >> > EXT_KEY(ZCMOP); >> > EXT_KEY(ZICBOZ); >> > + EXT_KEY(ZICNTR); >> > EXT_KEY(ZICOND); >> > EXT_KEY(ZIHINTNTL); >> > EXT_KEY(ZIHINTPAUSE); >> > + EXT_KEY(ZIHPM); >> > EXT_KEY(ZIMOP); >> > EXT_KEY(ZKND); >> > EXT_KEY(ZKNE); >> > >> > base-commit: dc1c8034e31b14a2e5e212104ec508aec44ce1b9 >>=20 >> Hello, >>=20 >> Can I get a review on this version of this patchset? > > Reviewed-by: Conor Dooley > > By the way, I totally missed this first time around because the v2 was > sent as a reply to v1 - it's pretty common for people to view their > mailbox sorted by thread, and sending new versions as a reply will bury > it. > > Cheers, > Conor. Thanks for the review! This is my first contribution to the Linux kernel, as you can tell :) Will keep in mind next time! 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