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Thu, 15 Aug 2024 06:32:16 -0700 (PDT) Received: from [100.64.0.1] ([147.124.94.167]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-39d1ec03005sm5645905ab.28.2024.08.15.06.32.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Aug 2024 06:32:16 -0700 (PDT) Message-ID: <686d61c4-e7ac-4dca-a7fd-decdd72e84d9@sifive.com> Date: Thu, 15 Aug 2024 08:32:13 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 0/9] Fix Allwinner D1 boot regression To: Thomas Gleixner , Emil Renner Berthing , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Anup Patel Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano References: <20240814145642.344485-1-emil.renner.berthing@canonical.com> <87jzgjnh9z.ffs@tglx> <87ttfmm2ns.ffs@tglx> <87plqalyd4.ffs@tglx> Content-Language: en-US From: Samuel Holland In-Reply-To: <87plqalyd4.ffs@tglx> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240815_063218_143423_3D835260 X-CRM114-Status: GOOD ( 22.58 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Thomas, Emil, On 2024-08-15 8:16 AM, Thomas Gleixner wrote: > On Thu, Aug 15 2024 at 05:14, Emil Renner Berthing wrote: >> Emil Renner Berthing wrote: >>> 6.11-rc3 + these reverts: https://us01.z.antigena.com/l/Er4kZWDmvL5-bLzHHJoZv0k71iwW2jCD5qNpiz0x0XdYY6oORF_nXh7U7jw6oubhi~32HI4i71jUW9v8~NvSvPeUWrdYx3WJBr2GPDUjOu6LYPCOBfR2dVQuMWvlNj4tDjXFp3QEQAmeawZflD4JrIJjtSYIbKfe6v-tgH7SEuHMeSSriU633Lv >>> 6.11-rc3 + Samuel's patch: https://us01.z.antigena.com/l/EULtAYky6ZvgqZ49KGS-WBsYTg~Ht1NoQtEYmUVb56ymS9jDagqYHLK90WDjnVt69GfB4IX5NSRQXmSfkNsTzB8lJmFvDihHQmGrsCv9FzlorD9yGfXDlQ6rG6vmn5BNDwlipmssGaOGfh9yko8n9ArWR4TLhEf~f9ODqme~NXXwA9DLLc9p >> >> I think this confirms what Charlie found here: >> https://lore.kernel.org/linux-riscv/ZoydV7vad5JWIcZb@ghost/ > > Yes. So the riscv timer is not working on this thing or it stops > somehow. That's correct. With the (firmware) devicetree that Emil is using, the OpenSBI firmware does not have a timer device, so it does not expose the (optional[1]) SBI time extension, and sbi_set_timer() does nothing. I wrote a patch (not submitted) to skip registering riscv_clock_event when the SBI time extension is unavailable, but this doesn't fully solve the issue either, because then we have no clockevent at all when check_unaligned_access_all_cpus() is called. How early in the boot process are we "required" to have a functional clockevent? Do we need to refactor check_unaligned_access_all_cpus() so it works on systems where the only clockevent is provided by a platform device? Regards, Samuel [1] https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/intro.adoc > Can you apply the debug patch below and check whether you see the > 'J: ....' output at all and if so whether it stops at some point. > > Thanks, > > tglx > > --- > --- a/kernel/time/timer.c > +++ b/kernel/time/timer.c > @@ -2459,6 +2459,9 @@ static void run_local_timers(void) > { > struct timer_base *base = this_cpu_ptr(&timer_bases[BASE_LOCAL]); > > + if (!(jiffies & 0xFF)) > + pr_info("J: %lx\n", jiffies); > + > hrtimer_run_queues(); > > for (int i = 0; i < NR_BASES; i++, base++) { > > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv