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Thu, 22 Dec 2022 14:33:28 -0800 (PST) Message-ID: <68fdb6e2-ed53-32ea-52ca-1e4d913ff7f3@linaro.org> Date: Thu, 22 Dec 2022 14:33:25 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break Content-Language: en-US To: Andy Chiu Cc: Vineet Gupta , Vincent Chen , Florian Weimer , Rich Felker , Andrew Waterman , Palmer Dabbelt , Kito Cheng , =?UTF-8?Q?Christoph_M=c3=bcllner?= , davidlt@rivosinc.com, Arnd Bergmann , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Philipp Tomsich , Szabolcs Nagy , Greentime Hu , Aaron Durbin , Andrew de los Reyes , linux-riscv , GNU C Library References: <1631497278-29829-1-git-send-email-vincent.chen@sifive.com> <1631497278-29829-3-git-send-email-vincent.chen@sifive.com> <871r5sd1zq.fsf@oldenburg.str.redhat.com> <20210913135247.GL13220@brightrain.aerifal.cx> <87sfy5ndid.fsf@oldenburg.str.redhat.com> <73c0124c-4794-6e40-460c-b26df407f322@rivosinc.com> <50c598a6-e3b3-3062-abe7-23a406067533@rivosinc.com> <7430f494-9b43-5e03-c1e9-6b83e2611a11@rivosinc.com> From: Richard Henderson In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221222_143331_316137_A38A7809 X-CRM114-Status: GOOD ( 10.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 12/22/22 10:33, Andy Chiu wrote: > I wrote a PoC patch for this and it has been pushed into the following git tree: > https://github.com/sifive/riscv-linux/tree/dev/andyc/for-next-v13 I had a look at your include/uapi/, and it looks good. Mere nits: > struct __riscv_q_ext_state { > __u64 f[64] __attribute__((aligned(16))); > __u32 fcsr; > /* > * Reserved for expansion of sigcontext structure. Currently zeroed > * upon signal, and must be zero upon sigreturn. > */ > __u32 reserved[3]; > }; > > struct __riscv_ctx_hdr { > __u32 magic; > __u32 size; > __u32 reserved; > }; Thinking about the _next_ extension on the chain, perhaps drop the 3rd word from here, so that (&hdr + 1) is 8-byte aligned (which may be enough depending on what the extension contains)? > struct __riscv_extra_ext_header { > __u64 ignored[64] __attribute__((aligned(16))); > __u32 padding; > /* > * Reserved for expansion of sigcontext structure. Currently zeroed > * upon signal, and must be zero upon sigreturn. > */ > struct __riscv_ctx_hdr hdr; > }; __u32 __padding[129] or __u64 __padding[65] depending on your answer to the above? It might reduce confusion to move (or replicate, for redundancy) the aligned(16) from the innermost __riscv_q_ext_state.f[] to the outermost sc_fpregs and/or sigcontext. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv