Re: [PATCH v2 3/3] irqchip/plic: add support for UltraRISC DP1000 PLIC

From: Vivian Wang <wangruikang@iscas.ac.cn>
To: Conor Dooley <conor@kernel.org>, Lucas Zampieri <lzampier@redhat.com>
Cc: linux-kernel@vger.kernel.org,
	Charles Mirabile <cmirabil@redhat.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Samuel Holland <samuel.holland@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Vivian Wang <dramforever@live.com>,
	linux-riscv@lists.infradead.org,
	Zhang Xincheng <zhangxincheng@ultrarisc.com>
Subject: Re: [PATCH v2 3/3] irqchip/plic: add support for UltraRISC DP1000 PLIC
Date: Tue, 14 Oct 2025 17:14:17 +0800	[thread overview]
Message-ID: <6b7c3c90-d3bd-4d75-9cc0-74d3945fbdfd@iscas.ac.cn> (raw)
In-Reply-To: <20251013-trimness-stainless-48343053f204@spud>

Hi Conor,

On 10/14/25 02:30, Conor Dooley wrote:
> On Mon, Oct 13, 2025 at 12:15:38PM +0100, Lucas Zampieri wrote:
>> From: Charles Mirabile <cmirabil@redhat.com>
>>
>> Add a new compatible for the plic found in UltraRISC DP1000 with a quirk to
>> work around a known hardware bug with IRQ claiming.
>>
>> When claiming an interrupt on the DP1000 PLIC all other interrupts must be
>> disabled before the claim register is accessed to prevent incorrect
>> handling of the interrupt.
>>
>> When the PLIC_QUIRK_CLAIM_REGISTER is present, during plic_handle_irq
>> the enable state of all interrupts is saved and then all interrupts
>> except for the first pending one are disabled before reading the claim
>> register. The interrupts are then restored before further processing of
>> the claimed interrupt continues.
>>
>> The driver matches on "ultrarisc,cp100-plic" to apply the quirk to all
>> SoCs using UR-CP100 cores, regardless of the specific SoC implementation.
> Why is that? I expect that you're doing that intentionally given the
> ultrarisc employee listed as a co-developer, but with only one SoC using
> this IP core it seems possible that this bug in the hardware could be
> fixed for other SoCs that are built using this IP core.
> Is there a plan to, for example, change the core version to UR-CP101
> when the bug is fixed?

I originally proposed to match on ultrarisc,cp100-plic under the
assumption that it would be the case.

Furthermore, it is my understanding that if the bug is fixed in, say,
UR-DP1001, then the PLIC node can simply be

    compatible = "ultrarisc,dp1001-plic", "sifive,plic-1.0.0";

I meant my reply that I had assumed this bug was associated with the
UR-CP100 core, but I should have stated so more clearly. 

Vivian "dramforever" Wang

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