Re: [PATCH v9 2/3] clk: canaan: Add clock driver for Canaan K230

[Xukai Wang <kingxukai@zohomail.com>]

On 2025/12/19 16:02, Jiayu Du wrote:
> On Thu, Nov 27, 2025 at 08:45:13PM +0800, Xukai Wang wrote:
>> This patch provides basic support for the K230 clock, which covers
>> all clocks in K230 SoC.
>>
>> The clock tree of the K230 SoC consists of a 24MHZ external crystal
>> oscillator, PLLs and an external pulse input for timerX, and their
>> derived clocks.
>>
>> Co-developed-by: Troy Mitchell <TroyMitchell988@gmail.com>
>> Signed-off-by: Troy Mitchell <TroyMitchell988@gmail.com>
>> Signed-off-by: Xukai Wang <kingxukai@zohomail.com>
>> ---
>>  drivers/clk/Kconfig    |    6 +
>>  drivers/clk/Makefile   |    1 +
>>  drivers/clk/clk-k230.c | 2443 ++++++++++++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 2450 insertions(+)
> ...
>> diff --git a/drivers/clk/clk-k230.c b/drivers/clk/clk-k230.c
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..8750e9cbac04f30e31d8f2eb395c9b49027ca278
>> --- /dev/null
>> +++ b/drivers/clk/clk-k230.c
>> @@ -0,0 +1,2443 @@
> ...
>> +
>> +K230_CLK_GATE_FORMAT(cpu0_src_gate,
>> +		     K230_CPU0_SRC_GATE,
>> +		     0, 0, 0, 0,
>> +		     &pll0_div2.hw);
> Core-related clocks of cpu0/cpu1 (src/plic/apb/noc_ddrcp4, etc.)
> lack protection flags, which risks accidental disabling.
>
> Recommend to replace the flag bits for all CPU0/CPU1 core clock
> nodes with `CLK_IS_CRITICAL`,like this:
> `0, 0, 0, 0,` -> `0, 0, CLK_IS_CRITICAL, 0,`
>
>> +
>> +K230_CLK_RATE_FORMAT(cpu0_src_rate,
>> +		     K230_CPU0_SRC_RATE,
>> +		     1, 16, 1, 0xF,
>> +		     16, 16, 0, 0x0,
>> +		     0x0, 31, mul, 0x0,
>> +		     false, 0,
>> +		     &cpu0_src_gate.clk.hw);
>> +
> same as above,`false, 0,` ->`false, CLK_IS_CRITICAL,`
>> +K230_CLK_RATE_FORMAT(cpu0_axi_rate,
>> +		     K230_CPU0_AXI_RATE,
>> +		     1, 1, 0, 0,
>> +		     1, 8, 6, 0x7,
>> +		     0x0, 31, div, 0x0,
>> +		     0, 0,
>> +		     &cpu0_src_rate.clk.hw);
>> +
> same as above,`0, 0,` ->`0, CLK_IS_CRITICAL,`
>> +K230_CLK_GATE_FORMAT(cpu0_plic_gate,
>> +		     K230_CPU0_PLIC_GATE,
>> +		     0x0, 9, 0, 0,
>> +		     &cpu0_src_rate.clk.hw);
>> +
> same as above,`0x0, 9, 0, 0,` -> `0x0, 9, CLK_IS_CRITICAL, 0,`
>> +K230_CLK_RATE_FORMAT(cpu0_plic_rate,
>> +		     K230_CPU0_PLIC_RATE,
>> +		     1, 1, 0, 0,
>> +		     1, 8, 10, 0x7,
>> +		     0x0, 31, div, 0x0,
>> +		     false, 0,
>> +		     &cpu0_plic_gate.clk.hw);
>> +
> same as above,`false, 0,` -> `false, CLK_IS_CRITICAL,`
>> +K230_CLK_GATE_FORMAT(cpu0_noc_ddrcp4_gate,
>> +		     K230_CPU0_NOC_DDRCP4_GATE,
>> +		     0x60, 7, 0, 0,
>> +		     &cpu0_src_rate.clk.hw);
>> +
> same as above,`0x60, 7, 0, 0,` -> `0x60, 7, CLK_IS_CRITICAL, 0,`
>> +K230_CLK_GATE_FORMAT(cpu0_apb_gate,
>> +		     K230_CPU0_APB_GATE,
>> +		     0x0, 13, 0, 0,
>> +		     &pll0_div4.hw);
>> +
> same as above,`0x0, 13, 0, 0,` -> `0x0, 13, CLK_IS_CRITICAL, 0,`
>> +K230_CLK_RATE_FORMAT(cpu0_apb_rate,
>> +		     K230_CPU0_APB_RATE,
>> +		     1, 1, 0, 0,
>> +		     1, 8, 15, 0x7,
>> +		     0x0, 31, div, 0x0,
>> +		     false, 0,
>> +		     &cpu0_apb_gate.clk.hw);
>> +
> same as above,`false, 0,` -> `false, CLK_IS_CRITICAL,`
>> +static const struct clk_parent_data k230_cpu1_src_mux_pdata[] = {
>> +	{ .hw = &pll0_div2.hw, },
>> +	{ .hw = &pll3.hw, },
>> +	{ .hw = &pll0.hw, },
>> +};
>> +
>> +K230_CLK_MUX_FORMAT(cpu1_src_mux,
>> +		    K230_CPU1_SRC_MUX,
>> +		    0x4, 1, 0x3,
>> +		    0, 0,
>> +		    k230_cpu1_src_mux_pdata);
>> +
> same as above,`0, 0,` -> `CLK_IS_CRITICAL, 0,`
>> +K230_CLK_GATE_FORMAT(cpu1_src_gate,
>> +		     K230_CPU1_SRC_GATE,
>> +		     0x4, 0, CLK_IGNORE_UNUSED, 0,
>> +		     &cpu1_src_mux.clk.hw);
>> +
> same as above,`0x4, 0, CLK_IGNORE_UNUSED, 0,` -> `0x4, 0, CLK_IS_CRITICAL, 0,`
>> +K230_CLK_RATE_FORMAT(cpu1_src_rate,
>> +		     K230_CPU1_SRC_GATE,
>> +		     1, 1, 0, 0,
>> +		     1, 8, 3, 0x7,
>> +		     0x4, 31, div, 0x0,
>> +		     false, 0,
>> +		     &cpu1_src_gate.clk.hw);
>> +
> same as above,`false, 0,` -> `false, CLK_IS_CRITICAL,`
>> +K230_CLK_RATE_FORMAT(cpu1_axi_rate,
>> +		     K230_CPU1_AXI_RATE,
>> +		     1, 1, 0, 0,
>> +		     1, 8, 12, 0x7,
>> +		     0x4, 31, div, 0x0,
>> +		     false, 0,
>> +		     &cpu1_src_rate.clk.hw);
>> +
> same as above,`false, 0,` -> `false, CLK_IS_CRITICAL,`
>> +K230_CLK_GATE_FORMAT(cpu1_plic_gate,
>> +		     K230_CPU1_PLIC_GATE,
>> +		     0x4, 15, CLK_IGNORE_UNUSED, 0,
>> +		     &cpu1_src_rate.clk.hw);
>> +
> same as above,`0x4, 15, CLK_IGNORE_UNUSED, 0,` -> `0x4, 15, CLK_IS_CRITICAL, 0,`
>> +K230_CLK_RATE_FORMAT(cpu1_plic_rate,
>> +		     K230_CPU1_PLIC_RATE,
>> +		     1, 1, 0, 0,
>> +		     1, 8, 16, 0x7,
>> +		     0x4, 31, div, 0x0,
>> +		     false, 0,
>> +		     &cpu1_plic_gate.clk.hw);
>> +
> same as above,`false, 0,` -> `false, CLK_IS_CRITICAL,`
>> +K230_CLK_GATE_FORMAT(cpu1_apb_gate,
>> +		     K230_CPU1_APB_GATE,
>> +		     0x4, 19, 0, 0,
>> +		     &pll0_div4.hw);
>> +
> same as above,`0x4, 19, 0, 0,` -> `0x4, 19, CLK_IS_CRITICAL, 0,`
>> +K230_CLK_RATE_FORMAT(cpu1_apb_rate,
>> +		     K230_CPU1_APB_RATE,
>> +		     1, 1, 0, 0,
>> +		     1, 8, 15, 0x7,
>> +		     0x0, 31, div, 0x0,
>> +		     false, 0,
>> +		     &cpu1_apb_gate.clk.hw);
>> +
> same as above,`false, 0,` -> `false, CLK_IS_CRITICAL,`
Thanks for the recommendation. I'll add the CLK_IS_CRITICAL flag to all
clk_gate clocks for CPU-related clocks, but not to the rate clocks, as
they don't need this flag.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv