Re: [PATCH v2 03/13] RISC-V: add ebreak instructions to definitions

Conor Dooley
2022-11-29T22:56:38Z

On Mon, Nov 28, 2022 at 11:26:22AM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@vrull.eu>
>
> kprobes need to match ebreaks instructions, so add the necessary

nit: ebreaks or ebreak instructions - but should it be stylised with
capitals to match the spec?

Otherwise this looks grand?
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> data to enable us to centralize that functionality.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> ---
> arch/riscv/include/asm/parse_asm.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/riscv/include/asm/parse_asm.h b/arch/riscv/include/asm/parse_asm.h
> index e3f87da108f4..e8303250f598 100644
> --- a/arch/riscv/include/asm/parse_asm.h
> +++ b/arch/riscv/include/asm/parse_asm.h
> @@ -144,7 +144,9 @@
> #define RVC_FUNCT3_C_JAL 0x1
> #define RVC_FUNCT4_C_JR 0x8
> #define RVC_FUNCT4_C_JALR 0x9
> +#define RVC_FUNCT4_C_EBREAK 0x9
>
> +#define RVG_FUNCT12_EBREAK 0x1
> #define RVG_FUNCT12_SRET 0x102
>
> #define RVG_MATCH_JALR (RV_ENCODE_FUNCT3(JALR) | RVG_OPCODE_JALR)
> @@ -155,6 +157,7 @@
> #define RVG_MATCH_BGE (RV_ENCODE_FUNCT3(BGE) | RVG_OPCODE_BRANCH)
> #define RVG_MATCH_BLTU (RV_ENCODE_FUNCT3(BLTU) | RVG_OPCODE_BRANCH)
> #define RVG_MATCH_BGEU (RV_ENCODE_FUNCT3(BGEU) | RVG_OPCODE_BRANCH)
> +#define RVG_MATCH_EBREAK (RV_ENCODE_FUNCT12(EBREAK) | RVG_OPCODE_SYSTEM)
> #define RVG_MATCH_SRET (RV_ENCODE_FUNCT12(SRET) | RVG_OPCODE_SYSTEM)
> #define RVC_MATCH_C_BEQZ (RVC_ENCODE_FUNCT3(C_BEQZ) | RVC_OPCODE_C1)
> #define RVC_MATCH_C_BNEZ (RVC_ENCODE_FUNCT3(C_BNEZ) | RVC_OPCODE_C1)
> @@ -162,6 +165,7 @@
> #define RVC_MATCH_C_JAL (RVC_ENCODE_FUNCT3(C_JAL) | RVC_OPCODE_C1)
> #define RVC_MATCH_C_JR (RVC_ENCODE_FUNCT4(C_JR) | RVC_OPCODE_C2)
> #define RVC_MATCH_C_JALR (RVC_ENCODE_FUNCT4(C_JALR) | RVC_OPCODE_C2)
> +#define RVC_MATCH_C_EBREAK (RVC_ENCODE_FUNCT4(C_EBREAK) | RVC_OPCODE_C2)
>
> #define RVG_MASK_JALR (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
> #define RVG_MASK_JAL (RV_INSN_OPCODE_MASK)
> @@ -177,6 +181,8 @@
> #define RVG_MASK_BGEU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
> #define RVC_MASK_C_BEQZ (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
> #define RVC_MASK_C_BNEZ (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
> +#define RVC_MASK_C_EBREAK 0xffff
> +#define RVG_MASK_EBREAK 0xffffffff
> #define RVG_MASK_SRET 0xffffffff
>
> #define __INSN_LENGTH_MASK _UL(0x3)
> --
> 2.35.1