From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Xingyu Wu <xingyu.wu@starfivetech.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Conor Dooley <conor+dt@kernel.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v5 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
Date: Tue, 13 Jun 2023 20:34:25 +0200 [thread overview]
Message-ID: <75508c4d-d86e-f88f-191f-dd870ebe7bd7@linaro.org> (raw)
In-Reply-To: <20230613125852.211636-4-xingyu.wu@starfivetech.com>
On 13/06/2023 14:58, Xingyu Wu wrote:
> Add optional PLL clock inputs from PLL clock generator.
Are you sure that PLLs are optional? Usually they are not...
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
> .../clock/starfive,jh7110-syscrg.yaml | 56 +++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
> index 84373ae31644..5536e5f9e20b 100644
> --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
> @@ -39,6 +39,33 @@ properties:
> - description: External TDM clock
> - description: External audio master clock
>
> + - items:
> + - description: Main Oscillator (24 MHz)
> + - description: GMAC1 RMII reference or GMAC1 RGMII RX
> + - description: External I2S TX bit clock
> + - description: External I2S TX left/right channel clock
> + - description: External I2S RX bit clock
> + - description: External I2S RX left/right channel clock
> + - description: External TDM clock
> + - description: External audio master clock
> + - description: PLL0
> + - description: PLL1
> + - description: PLL2
Add these three to the existing entry with minItems.
> +
> + - items:
> + - description: Main Oscillator (24 MHz)
> + - description: GMAC1 RMII reference
> + - description: GMAC1 RGMII RX
> + - description: External I2S TX bit clock
> + - description: External I2S TX left/right channel clock
> + - description: External I2S RX bit clock
> + - description: External I2S RX left/right channel clock
> + - description: External TDM clock
> + - description: External audio master clock
> + - description: PLL0
> + - description: PLL1
> + - description: PLL2
Add these three to the existing entry with minItems.
> +
> clock-names:
> oneOf:
> - items:
> @@ -64,6 +91,35 @@ properties:
> - const: tdm_ext
> - const: mclk_ext
>
> + - items:
> + - const: osc
> + - enum:
> + - gmac1_rmii_refin
> + - gmac1_rgmii_rxin
> + - const: i2stx_bclk_ext
> + - const: i2stx_lrck_ext
> + - const: i2srx_bclk_ext
> + - const: i2srx_lrck_ext
> + - const: tdm_ext
> + - const: mclk_ext
> + - const: pll0_out
> + - const: pll1_out
> + - const: pll2_out
Add these three to the existing entry with minItems.
> +
> + - items:
> + - const: osc
> + - const: gmac1_rmii_refin
> + - const: gmac1_rgmii_rxin
> + - const: i2stx_bclk_ext
> + - const: i2stx_lrck_ext
> + - const: i2srx_bclk_ext
> + - const: i2srx_lrck_ext
> + - const: tdm_ext
> + - const: mclk_ext
> + - const: pll0_out
> + - const: pll1_out
> + - const: pll2_out
Add these three to the existing entry with minItems.
Best regards,
Krzysztof
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next prev parent reply other threads:[~2023-06-13 18:34 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-13 12:58 [PATCH v5 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-06-13 12:58 ` [PATCH v5 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-06-13 19:06 ` Conor Dooley
2023-06-13 12:58 ` [PATCH v5 2/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-06-13 18:31 ` Krzysztof Kozlowski
2023-06-28 6:44 ` Xingyu Wu
2023-06-28 17:34 ` Conor Dooley
2023-06-29 6:42 ` Xingyu Wu
2023-06-29 9:01 ` Conor Dooley
2023-06-13 18:32 ` Krzysztof Kozlowski
2023-06-13 12:58 ` [PATCH v5 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-06-13 18:34 ` Krzysztof Kozlowski [this message]
2023-06-13 19:17 ` Conor Dooley
2023-06-13 12:58 ` [PATCH v5 4/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-06-13 12:58 ` [PATCH v5 5/7] clk: starfive: jh7110-sys: Add PLL clocks source from DTS Xingyu Wu
2023-06-13 12:58 ` [PATCH v5 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu
2023-06-13 19:58 ` Conor Dooley
2023-06-13 12:58 ` [PATCH v5 7/7] riscv: dts: starfive: jh7110: Add PLL clock source in SYSCRG node Xingyu Wu
2023-06-13 19:55 ` Conor Dooley
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