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Wed, 02 Mar 2022 13:01:19 +0000 MIME-Version: 1.0 Date: Wed, 02 Mar 2022 13:01:19 +0000 From: Marc Zyngier To: Niklas Cassel Cc: Thomas Gleixner , Palmer Dabbelt , Paul Walmsley , Albert Ou , damien.lemoal@opensource.wdc.com, linux-riscv@lists.infradead.org Subject: Re: [PATCH v2 2/2] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode In-Reply-To: <20220301171317.3109161-3-Niklas.Cassel@wdc.com> References: <20220301171317.3109161-1-Niklas.Cassel@wdc.com> <20220301171317.3109161-3-Niklas.Cassel@wdc.com> User-Agent: Roundcube Webmail/1.4.13 Message-ID: <7ac17ea72a45f201c93b477657b6f766@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: Niklas.Cassel@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, damien.lemoal@opensource.wdc.com, linux-riscv@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220302_050122_867756_6778FBBF X-CRM114-Status: GOOD ( 22.74 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 2022-03-01 17:13, Niklas Cassel wrote: > From: Niklas Cassel > > When detecting a context for a privilege mode different from the > current > running privilege mode, we simply skip to the next context register. > > This means that we never clear the S-mode enable bits when running in > M-mode. > > On canaan k210, a bunch of S-mode interrupts are enabled by the > bootrom. > These S-mode specific interrupts should never trigger, since we never > set > the mie.SEIE bit in the parent interrupt controller (riscv-intc). > > However, we will be able to see the mip.SEIE bit set as pending. > > This isn't a good default when CONFIG_RISCV_M_MODE is set, since in > that > case we will never enter a lower privilege mode (e.g. S-mode). > > Let's clear the S-mode enable bits when running the kernel in M-mode, > such > that we won't have a interrupt pending bit set, which we will never > clear. > > Signed-off-by: Niklas Cassel > --- > drivers/irqchip/irq-sifive-plic.c | 26 +++++++++++++++++++++----- > 1 file changed, 21 insertions(+), 5 deletions(-) > > diff --git a/drivers/irqchip/irq-sifive-plic.c > b/drivers/irqchip/irq-sifive-plic.c > index fc9da94eb816..e6193d66c0ae 100644 > --- a/drivers/irqchip/irq-sifive-plic.c > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -81,17 +81,23 @@ static int plic_parent_irq __ro_after_init; > static bool plic_cpuhp_setup_done __ro_after_init; > static DEFINE_PER_CPU(struct plic_handler, plic_handlers); > > -static inline void plic_toggle(struct plic_handler *handler, > - int hwirq, int enable) > +static inline void __plic_toggle(void __iomem *enable_base, > + int hwirq, int enable) While you're at it, please drop the inline attributes. They really serve no purpose, as that's the job of the compiler. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv