From: Kefeng Wang <wangkefeng.wang@huawei.com>
To: Anup Patel <anup@brainfault.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Albert Ou <aou@eecs.berkeley.edu>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
hulkci@huawei.com, Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
linux-riscv <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val
Date: Wed, 20 May 2020 10:57:38 +0800 [thread overview]
Message-ID: <7bfb95d7-93ff-e649-06c0-dc96bedcdb1d@huawei.com> (raw)
In-Reply-To: <CAAhSdy2wsnkYMLpT1_2OAjr334t6dAy9LCPNefC=h+aPuRqFrg@mail.gmail.com>
On 2020/5/20 9:14, Anup Patel wrote:
> On Tue, May 19, 2020 at 7:21 PM Daniel Lezcano
> <daniel.lezcano@linaro.org> wrote:
>> On 19/05/2020 14:39, Kefeng Wang wrote:
>>> On 2020/5/19 4:23, Daniel Lezcano wrote:
>>>> Hi Kefeng,
>>>>
>>>> On 18/05/2020 17:40, Kefeng Wang wrote:
>>>>> On 2020/5/18 22:09, Daniel Lezcano wrote:
>>>>>> On 13/05/2020 23:14, Palmer Dabbelt wrote:
>>>>>>> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com
>>>>>>> wrote:
>>>>>>>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>>>>>>>>
>>>>>>>> Reported-by: Hulk Robot <hulkci@huawei.com>
>>>>>>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>>>>>>>> ---
>>>>>>>> drivers/clocksource/timer-riscv.c | 1 +
>>>>>>>> 1 file changed, 1 insertion(+)
>>>>>>>>
>>>>>>>> diff --git a/drivers/clocksource/timer-riscv.c
>>>>>>>> b/drivers/clocksource/timer-riscv.c
>>>>>>>> index c4f15c4068c0..071b8c144027 100644
>>>>>>>> --- a/drivers/clocksource/timer-riscv.c
>>>>>>>> +++ b/drivers/clocksource/timer-riscv.c
>>>>>>>> @@ -19,6 +19,7 @@
>>>>>>>>
>>>>>>>> u64 __iomem *riscv_time_cmp;
>>>>>>>> u64 __iomem *riscv_time_val;
>>>>>>>> +EXPORT_SYMBOL(riscv_time_val);
>>>>>>>>
>>>>>>>> static inline void mmio_set_timer(u64 val)
>>>>>>>> {
>>>>>>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>>>>> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>>>>>
>>>>>>> Adding the clocksource maintainers. Let me know if you want this
>>>>>>> through my
>>>>>>> tree, I'm assuming you want it through your tree.
>>>>>> How can we end up by an export symbol here ?!
>>>>> Hi Danile,
>>>> s/Danile/Daniel/
>>> Sorry for typing error.
>>>>> Found this build error when CONFIG_RISCV_M_MODE=y and CONFIG_RISCV_SBI
>>>>> is not,
>>>>>
>>>>> see patch "4f9bbcefa142 riscv: add support for MMIO access to the timer
>>>>> registers"
>>>> Thanks for the pointer.
>>>>
>>>> The question still remains, how do we end up with this EXPORT_SYMBOL?
>>>>
>>>> There is something wrong if the fix is an EXPORT_SYMBOL for a global
>>>> variable.
>>> Not very clear, there are some global variable( eg, acpi_disabled,
>>> memstart_addr in arm64,) is exported by EXPORT_SYMBOL, do you mean that
>>> export riscv_time_val is wrong way?
>> I do not maintain acpi neither arm64.mm.
>>
>> AFAICT, riscv_time_val is globally declared in
>> drivers/clocksource/timer-riscv.c
>>
>> The driver does not use this variable at all. Then there is a readl on
>> it in the header file arch/riscv/include/asm/timex.h
>>
>> And finally it is initialized in arch/riscv/kernel/clint.c
>>
>> Same thing for riscv_time_cmp.
>>
>> The correct fix is to initialize the variables in the place where they
>> belong to (drivers/clocksource/timer-riscv.c), create a function to read
>> their content and export-symbol-gpl the function.
ok, it's better. thanks for your explanation.
> I agree with Daniel. Exporting riscv_time_val is a temporary fix.
yes. it's only for build, let's wait for Anup's patch.
>
> The problem is timer-riscv.c is pretty convoluted right now. It is
> implementing two different clocksources and clockevents in one-place.
>
> I think we need two separate drivers for RISC-V world.
>
> 1. timer-riscv: This for regular S-mode kernel with MMU. The clocksource
> will use TIME CSR and the clockevent device will use SBI calls.
>
> 2. timer-clint: This for M-mode kernel without MMU (or NoMMU kernel).
> The clocksource will use MMIO counter for clocksource and the
> clockevent device will use MMIO compare registers.
>
> I will send a patch to have a separate timer-clint driver under
> drivers/clocksource. (@Daniel, I hope you will be fine with this?)
> Regards,
> Anup
>
>>
>> --
>> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>>
>> Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
>> <http://twitter.com/#!/linaroorg> Twitter |
>> <http://www.linaro.org/linaro-blog/> Blog
> .
>
next prev parent reply other threads:[~2020-05-20 2:58 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 2:19 [PATCH 00/10] riscv: make riscv build happier Kefeng Wang
2020-05-11 2:19 ` [PATCH 01/10] riscv: Fix unmet direct dependencies built based on SOC_VIRT Kefeng Wang
2020-05-13 21:14 ` Palmer Dabbelt
2020-05-11 2:19 ` [PATCH 02/10] riscv: stacktrace: Fix undefined reference to `walk_stackframe' Kefeng Wang
2020-05-11 2:19 ` [PATCH 03/10] riscv: Add pgprot_writecombine/device and PAGE_SHARED defination if NOMMU Kefeng Wang
2020-05-11 2:19 ` [PATCH 04/10] riscv: Fix print_vm_layout build error " Kefeng Wang
2020-05-14 10:10 ` Alex Ghiti
2020-05-14 11:42 ` Kefeng Wang
2020-05-14 11:53 ` [PATCH v2] " Kefeng Wang
2020-05-20 22:49 ` Palmer Dabbelt
2020-05-11 2:19 ` [PATCH 05/10] riscv: Disable ARCH_HAS_DEBUG_WX " Kefeng Wang
2020-05-13 21:14 ` Palmer Dabbelt
2020-05-14 8:26 ` Kefeng Wang
2020-05-11 2:19 ` [PATCH 06/10] riscv: Disable ARCH_HAS_DEBUG_VIRTUAL " Kefeng Wang
2020-05-11 2:19 ` [PATCH 07/10] riscv: Make SYS_SUPPORTS_HUGETLBFS depends on MMU Kefeng Wang
2020-05-13 21:14 ` Palmer Dabbelt
2020-05-11 2:19 ` [PATCH 08/10] riscv: pgtable: Fix __kernel_map_pages build error if NOMMU Kefeng Wang
2020-05-11 2:20 ` [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val Kefeng Wang
2020-05-13 21:14 ` Palmer Dabbelt
2020-05-18 14:09 ` Daniel Lezcano
2020-05-18 15:40 ` Kefeng Wang
2020-05-18 20:23 ` Daniel Lezcano
2020-05-19 12:39 ` Kefeng Wang
2020-05-19 13:51 ` Daniel Lezcano
2020-05-20 1:14 ` Anup Patel
2020-05-20 2:57 ` Kefeng Wang [this message]
2020-05-11 2:20 ` [PATCH 10/10] riscv: mmiowb: Fix implicit declaration of function 'smp_processor_id' Kefeng Wang
2020-05-13 21:14 ` [PATCH 00/10] riscv: make riscv build happier Palmer Dabbelt
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