Re: [RESEND PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events

From: Samuel Holland <samuel.holland@sifive.com>
To: Atish Patra <atishp@atishpatra.org>
Cc: linux-riscv@lists.infradead.org,
	Arnaldo Carvalho de Melo <acme@redhat.com>,
	Ian Rogers <irogers@google.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	linux-perf-users@vger.kernel.org,
	Mark Rutland <mark.rutland@arm.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	linux-kernel@vger.kernel.org, Jiri Olsa <jolsa@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Atish Patra <atishp@rivosinc.com>
Subject: Re: [RESEND PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events
Date: Fri, 21 Mar 2025 15:57:09 -0500	[thread overview]
Message-ID: <7c42afed-e877-4136-a6d6-8ebc9864cc04@sifive.com> (raw)
In-Reply-To: <CAOnJCUKUY8YQ0UtLa39EkGEjckiOqdnuqEsf2ak4Dcp779iY+Q@mail.gmail.com>

Hi Atish,

On 2025-03-21 1:31 PM, Atish Patra wrote:
> On Fri, Mar 7, 2025 at 1:19 AM Samuel Holland <samuel.holland@sifive.com> wrote:
>> On 2025-03-01 3:21 AM, Atish Patra wrote:
>>> On Wed, Feb 19, 2025 at 1:27 PM Namhyung Kim <namhyung@kernel.org> wrote:
>>>> On Wed, Feb 12, 2025 at 05:21:33PM -0800, Samuel Holland wrote:
>>>>> This series updates the PMU event JSON files to add support for newer
>>>>> SiFive CPUs, including those used in the HiFive Premier P550 board.
>>>>> Since most changes are incremental, symbolic links are used when a set
>>>>> of events is unchanged from the previous CPU series.
>>>>>
>>>>> I originally sent this series about a year ago[1], but received no
>>>>> feedback. The P550 board is now available (and I have tested this series
>>>>> on it), so it would be good to get perf support for it upstream.
>>>>>
>>>>> [1]: https://lore.kernel.org/linux-perf-users/20240509021531.680920-1-samuel.holland@sifive.com/
>>>>>
>>>
>>> Tested the patches that are part of sifive's release tree for p550.
>>> Both perf stat/record seems to work fine
>>> for a bunch of events.
>>>
>>> Based on that
>>> Tested-by: Atish Patra <atishp@rivosinc.com>
>>
>> Thanks for testing!
>>
>>> @Samuel Holland : perf report that the following two events are not
>>> supported on the p550 board.
>>>
>>> cycle and instruction count:
>>>   core_clock_cycles
>>>        [Counts core clock cycles]
>>>   instructions_retired
>>>        [Counts instructions retired]
>>>
>>> I assumed that these are raw events cycle/instruction retired events
>>> that can support
>>> perf sampling as well. Maybe I am missing something ? DT binding ?
>>
>> perf is correct. Those two events are not supported on P550, only by the newer
>> cores (bulled-0d and p650). Yes, those are aliases of cycles and instructions
>> that were added to support sampling.
>>
> 
> Thanks for the confirmation. Are there other events that can be used to sample
> instruction count on P550 ? I did not find anything in the perf list
> or the json file.
> I am not sure if I missed something.

Likely the closest approximation is ORing together the instruction class
retirement events from instruction.json: cpu/r0x3fffe00/. The difference between
that and "instructions" looks to be well within 1% for CPU-intensive workloads.
Maybe it makes sense to add an entry for this combination in the JSON? Would it
be appropriate to call it "instructions_retired"? The same thing could be done
for the older SiFive cores.

Regards,
Samuel

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