Re: [PATCH] drivers/perf: riscv: Keep the fixed counter counting

[Atish Patra <atish.patra@linux.dev>]

On 2/9/26 4:36 AM, cp0613@linux.alibaba.com wrote:
> On Wed, 4 Feb 2026 01:17:25 -0800, atish.patra@linux.dev wrote:
>
>>> The RISC-V SBI PMU driver disables all PMU counters during initialization
>>> via pmu_sbi_stop_all. For fixed counters CYCLE, TIME and INSTRET, this is
>>> unnecessary for the following two reasons:
>>>
>>> 1. Some kernel driver code may directly read CYCLE and INSTRET to perform
>>>      simple performance analysis.
>> Is this for some debugging purpose to read the instret/cycle count at
>> boot time or real use case for driver performance analysis ?
>>
>> If it is the latter, that will be problematic for various reasons such
>> as context switching will lead to inaccurate numbers.
> Hi Atish,
>
> Thanks for the reminder, but I might not be able to provide specific scenarios
> due to our niche usage. Therefore, let's just discuss the legacy usage of
> sysctl_perf_user_access.
>
>>> 2. In legacy mode, user space directly reads CYCLE and INSTRET. (echo 2 >
>>>      /proc/sys/kernel/perf_user_access)
>>>
>>> Therefore, We keep counting CYCLE, TIME and INSTRET.
>>>
>>> Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
>>> ---
>>>    drivers/perf/riscv_pmu_sbi.c | 3 +++
>>>    1 file changed, 3 insertions(+)
>>>
>>> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
>>> index 7dd282da67ce..93aaab324443 100644
>>> --- a/drivers/perf/riscv_pmu_sbi.c
>>> +++ b/drivers/perf/riscv_pmu_sbi.c
>>> @@ -899,6 +899,9 @@ static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask)
>>>    
>>>    static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu)
>>>    {
>>> + /* We keep counting CYCLE, TIME and INSTRET. */
>>> + pmu->cmask &= ~0x7;
>>> +
>> This is incorrect. The cmask should be set based on the perf_user_access
>> value. We should not continue counting the CYCLE/INSTRET when legacy
>> mode is not set. if (sysctl_perf_user_access == SYSCTL_LEGACY)
>> csr_write(CSR_SCOUNTEREN, 0x7); else csr_write(CSR_SCOUNTEREN, 0x2);
> I have a slightly different understanding here. Regarding perf_user_access, I think
> it is only used to control user mode access permissions to CYCLE, TIME, and INSTRET
> (via SCOUNTEREN), but whether the counters themselves are in a counting state is
> another issue (via MCOUNTINHIBIT). I think the cmask in pmu_sbi_stop_all should
> represent a counter to stop the counting, rather than a permission configuration.
>
> The problem we are currently encountering is that even when switching to LEGACY mode,
> CYCLE and INSTRET are not counting, so we want to change this default behavior so
> that these three fixed counters are always in counting.

Ahh. We should just enable counting when you user turn on the legacy 
mode not the default
behavior.

> Sorry for the late reply. I've reviewed some previous related discussions, and it
> seems that using time is more reasonable between cycle and time. However, for some
> small code snippets, there is a need to use cycle and instant (at least instant),
> so keeping them constantly counting doesn't seem to have any downsides.

This thread slipped through cracks unfortunately. Apologies for the late 
reply as well.
I understand the usage which is quick debugging purpose only. So we 
should not introduce
side channel exploits in production code for that purpose.
We keep revisiting topic even after numerous discussion in the past.

We must ensure that legacy mode is the only way where this is enabled.

> Thanks,
> Pei
>
>>>     /*
>>>      * No need to check the error because we are disabling all the counters
>>>      * which may include counters that are not enabled yet.

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