[RFC PATCH v2 0/9] Redo PolarFire SoC's mailbox/clock devicestrees and related code

Conor Dooley
2025-03-21T17:23:23Z

(Back to RFC again, as I'm really just wanting to hear from Stephen on
what I did with the regmap clocks, and if it was what he was looking
for)

Yo,

Here's something that I've been mulling over for a while, since I
started to understand how devicetree stuff was "meant" to be done.
There'd been little reason to actually press forward with it, because it
is fairly disruptive. I've finally opted to do it, because a user has
come along with a hwmon driver that needs to access the same register
region as the mailbox and the author is not keen on using the aux bus,
and because I do not want the new pic64gx SoC that's based on PolarFire
SoC to use bindings etc that I know to be incorrect.

Given backwards compatibility needs to be maintained, this patch series
isn't the prettiest thing I have ever written. The reset driver needs to
retain support for the auxiliary bus, which looks a bit mess, but not
much can be done there. The mailbox and clock drivers both have to have
an "old probe" function to handle the old layout. Thankfully in the
clock driver, regmap support can be used to identically
handle both old and new devicetree formats - but using a regmap in the
mailbox driver was only really possible for the new format, so the code
there is unfortunately a bit of an if/else mess that I'm both not proud
of, nor really sure is worth "improving".

The series should be pretty splitable per subsystem, only the dts change
has some sort of dependency, but I'll not be applying that till
everything else is in Linus' tree, so that's not a big deal.

I don't really want this stuff in stable, hence a lack of cc: stable
anywhere here, since what's currently in the tree works fine for the
currently supported hardware.

AFAIK, the only other project affected here is U-Boot, which I have
already modified to support the new format.

I previously submitted this as an RFC, only to Lee and the dt list, in
order to get some feedback on the syscon/mfd bindings:
https://lore.kernel.org/all/20240815-shindig-bunny-fd42792d638a@spud/
I'm not really going to bother with a proper changelog, since that was
submitted with lots of WIP code to get answers to some questions. The
main change was "removing" some of the child nodes of the syscons.

and as a "real" series where discussion lead to me dropping use of the
amlogic clk-regmap support:
https://lore.kernel.org/linux-clk/20241002-private-unequal-33cfa6101338@spud/
As a result of that, I've implemented what I think Stephen was asking
for - but I'm not at all sure that it is..

Cheers,
Conor.

CC: Conor Dooley <conor.dooley@microchip.com>
CC: Daire McNamara <daire.mcnamara@microchip.com>
CC: pierre-henry.moussay@microchip.com
CC: valentina.fernandezalanis@microchip.com
CC: Michael Turquette <mturquette@baylibre.com>
CC: Stephen Boyd <sboyd@kernel.org>
CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
CC: Jassi Brar <jassisinghbrar@gmail.com>
CC: Lee Jones <lee@kernel.org>
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: Philipp Zabel <p.zabel@pengutronix.de>
CC: linux-riscv@lists.infradead.org
CC: linux-clk@vger.kernel.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org

Conor Dooley (9):
dt-bindings: mfd: syscon document the control-scb syscon on PolarFire
SoC
dt-bindings: soc: microchip: document the simple-mfd syscon on
PolarFire SoC
soc: microchip: add mfd drivers for two syscon regions on PolarFire
SoC
reset: mpfs: add non-auxiliary bus probing
dt-bindings: clk: microchip: mpfs: remove first reg region
riscv: dts: microchip: fix mailbox description
riscv: dts: microchip: convert clock and reset to use syscon
clk: divider, gate: create regmap-backed copies of gate and divider
clocks
clk: microchip: mpfs: use regmap clock types

.../bindings/clock/microchip,mpfs-clkcfg.yaml | 36 ++-
.../devicetree/bindings/mfd/syscon.yaml | 2 +
.../microchip,mpfs-mss-top-sysreg.yaml | 49 ++++
arch/riscv/boot/dts/microchip/mpfs.dtsi | 34 ++-
drivers/clk/Kconfig | 8 +
drivers/clk/Makefile | 2 +
drivers/clk/clk-divider-regmap.c | 270 ++++++++++++++++++
drivers/clk/clk-gate-regmap.c | 253 ++++++++++++++++
drivers/clk/clk-gate.c | 5 +-
drivers/clk/microchip/Kconfig | 4 +
drivers/clk/microchip/clk-mpfs.c | 151 ++++++----
drivers/reset/reset-mpfs.c | 81 ++++--
drivers/soc/microchip/Kconfig | 13 +
drivers/soc/microchip/Makefile | 1 +
drivers/soc/microchip/mpfs-control-scb.c | 45 +++
drivers/soc/microchip/mpfs-mss-top-sysreg.c | 48 ++++
include/linux/clk-provider.h | 120 ++++++++
17 files changed, 1026 insertions(+), 96 deletions(-)
create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
create mode 100644 drivers/clk/clk-divider-regmap.c
create mode 100644 drivers/clk/clk-gate-regmap.c
create mode 100644 drivers/soc/microchip/mpfs-control-scb.c
create mode 100644 drivers/soc/microchip/mpfs-mss-top-sysreg.c