From: Damien Le Moal <damien.lemoal@opensource.wdc.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>,
Rob Herring <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Lewis Hanly <lewis.hanly@microchip.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Conor Dooley <conor.dooley@microchip.com>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>
Subject: Re: [PATCH 2/9] riscv: dts: canaan: Group tuples in interrupt properties
Date: Fri, 26 Nov 2021 13:42:40 +0900 [thread overview]
Message-ID: <853018bd-8c5e-4a03-9876-ca9f8a412ea5@opensource.wdc.com> (raw)
In-Reply-To: <20211125153131.163533-3-geert@linux-m68k.org>
On 2021/11/26 0:31, Geert Uytterhoeven wrote:
> To improve human readability and enable automatic validation, the tuples
> in the various properties containing interrupt specifiers should be
> grouped.
>
> Fix this by grouping the tuples of "interrupts" and
> "interrupts-extended" properties using angle brackets.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> arch/riscv/boot/dts/canaan/k210.dtsi | 23 ++++++++++++-----------
> 1 file changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
> index 5e8ca8142482153b..56f57118c633b91a 100644
> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
> @@ -103,8 +103,8 @@ rom0: nvmem@1000 {
> clint0: timer@2000000 {
> compatible = "canaan,k210-clint", "sifive,clint0";
> reg = <0x2000000 0xC000>;
> - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
> - &cpu1_intc 3 &cpu1_intc 7>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>;
> };
>
> plic0: interrupt-controller@c000000 {
> @@ -113,7 +113,7 @@ plic0: interrupt-controller@c000000 {
> compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
> reg = <0xC000000 0x4000000>;
> interrupt-controller;
> - interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>;
> riscv,ndev = <65>;
> };
>
> @@ -130,10 +130,11 @@ gpio0: gpio-controller@38001000 {
> compatible = "canaan,k210-gpiohs", "sifive,gpio0";
> reg = <0x38001000 0x1000>;
> interrupt-controller;
> - interrupts = <34 35 36 37 38 39 40 41
> - 42 43 44 45 46 47 48 49
> - 50 51 52 53 54 55 56 57
> - 58 59 60 61 62 63 64 65>;
> + interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>,
> + <41>, <42>, <43>, <44>, <45>, <46>, <47>,
> + <48>, <49>, <50>, <51>, <52>, <53>, <54>,
> + <55>, <56>, <57>, <58>, <59>, <60>, <61>,
> + <62>, <63>, <64>, <65>;
> gpio-controller;
> ngpios = <32>;
> };
> @@ -141,7 +142,7 @@ gpio0: gpio-controller@38001000 {
> dmac0: dma-controller@50000000 {
> compatible = "snps,axi-dma-1.01a";
> reg = <0x50000000 0x1000>;
> - interrupts = <27 28 29 30 31 32>;
> + interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
> #dma-cells = <1>;
> clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
> clock-names = "core-clk", "cfgr-clk";
> @@ -316,7 +317,7 @@ fpioa: pinmux@502b0000 {
> timer0: timer@502d0000 {
> compatible = "snps,dw-apb-timer";
> reg = <0x502D0000 0x100>;
> - interrupts = <14 15>;
> + interrupts = <14>, <15>;
> clocks = <&sysclk K210_CLK_TIMER0>,
> <&sysclk K210_CLK_APB0>;
> clock-names = "timer", "pclk";
> @@ -326,7 +327,7 @@ timer0: timer@502d0000 {
> timer1: timer@502e0000 {
> compatible = "snps,dw-apb-timer";
> reg = <0x502E0000 0x100>;
> - interrupts = <16 17>;
> + interrupts = <16>, <17>;
> clocks = <&sysclk K210_CLK_TIMER1>,
> <&sysclk K210_CLK_APB0>;
> clock-names = "timer", "pclk";
> @@ -336,7 +337,7 @@ timer1: timer@502e0000 {
> timer2: timer@502f0000 {
> compatible = "snps,dw-apb-timer";
> reg = <0x502F0000 0x100>;
> - interrupts = <18 19>;
> + interrupts = <18>, <19>;
> clocks = <&sysclk K210_CLK_TIMER2>,
> <&sysclk K210_CLK_APB0>;
> clock-names = "timer", "pclk";
>
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Tested-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
--
Damien Le Moal
Western Digital Research
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next prev parent reply other threads:[~2021-11-26 4:42 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-25 15:31 [PATCH 0/9] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
2021-11-25 15:31 ` [PATCH 1/9] riscv: dts: canaan: Fix SPI FLASH node names Geert Uytterhoeven
2021-11-26 4:41 ` Damien Le Moal
2021-11-26 9:54 ` Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 2/9] riscv: dts: canaan: Group tuples in interrupt properties Geert Uytterhoeven
2021-11-26 4:42 ` Damien Le Moal [this message]
2021-11-26 9:53 ` Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 3/9] riscv: dts: microchip: mpfs: Drop empty chosen node Geert Uytterhoeven
2021-11-26 9:53 ` Krzysztof Kozlowski
2021-11-26 9:57 ` Geert Uytterhoeven
2021-11-26 11:45 ` Conor.Dooley
2021-11-25 15:31 ` [PATCH 4/9] riscv: dts: microchip: Group tuples in interrupt properties Geert Uytterhoeven
2021-11-26 8:42 ` Conor.Dooley
2021-12-03 14:38 ` Geert Uytterhoeven
2021-12-03 15:17 ` Conor.Dooley
2021-11-26 9:52 ` Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 5/9] riscv: dts: microchip: mpfs: Fix PLIC node Geert Uytterhoeven
2021-11-26 9:49 ` Krzysztof Kozlowski
2021-11-26 11:49 ` Conor.Dooley
2021-11-25 15:31 ` [PATCH 6/9] riscv: dts: microchip: mpfs: Fix reference clock node Geert Uytterhoeven
2021-11-26 9:48 ` Krzysztof Kozlowski
2021-11-26 10:14 ` Conor.Dooley
2021-11-26 10:47 ` Conor.Dooley
2021-12-03 15:29 ` Conor.Dooley
2021-12-03 15:42 ` Krzysztof Kozlowski
2021-12-03 15:49 ` Geert Uytterhoeven
2021-11-25 15:31 ` [PATCH 7/9] riscv: dts: sifive: Group tuples in register properties Geert Uytterhoeven
2021-11-26 9:46 ` Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 8/9] riscv: dts: sifive: Group tuples in interrupt properties Geert Uytterhoeven
2021-11-26 9:46 ` Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 9/9] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values Geert Uytterhoeven
2021-11-26 9:46 ` Krzysztof Kozlowski
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