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From: Paul Walmsley <pjw@kernel.org>
To: Ben Dooks <ben.dooks@codethink.co.uk>
Cc: linux-riscv@lists.infradead.org, pjw@kernel.org,
	palmer@dabbelt.com,  aou@eecs.berkeley.edu,
	ajones@ventanamicro.com
Subject: Re: [PATCH] riscv: asm: use .insn for making custom instructioons
Date: Fri, 17 Oct 2025 12:25:20 -0600 (MDT)	[thread overview]
Message-ID: <857ab359-4eef-73c6-0085-7c3bd5dba687@kernel.org> (raw)
In-Reply-To: <20251017165527.701934-1-ben.dooks@codethink.co.uk>

Hi Ben,

On Fri, 17 Oct 2025, Ben Dooks wrote:

> Using .word breaks with big endian builds, making something which
> is not a valid or worse an instruction or pair that does something
> which is not intended.
> 
> It would seem sensible to add an ASM_INSN() wrapper for anyone to
> use for hand assembly of instructions.

Looking at the GNU as documentation for RISC-V:

  https://sourceware.org/binutils/docs/as/RISC_002dV_002dDirectives.html

it seems that RISC-V .insn supports several argument formats that .4byte 
wouldn't.  So it seems this is only applicable for opcodes specified as 
hex bytes?  Might be worth adding that to the macro name in some form.  

Also, looks like this is missing the opcodes added in commit 
1d4ce63e338fc.  If you update this one, could you please add those as 
well?

thanks


- Paul

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  reply	other threads:[~2025-10-17 18:25 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-17 16:55 [PATCH] riscv: asm: use .insn for making custom instructioons Ben Dooks
2025-10-17 18:25 ` Paul Walmsley [this message]
2025-10-23 17:06   ` Ben Dooks
2025-10-17 18:27 ` Andrew Jones
2025-10-23 17:15   ` Ben Dooks
2025-10-18  4:50 ` Maciej W. Rozycki
2025-10-23 17:12   ` Ben Dooks

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