From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE200C48291 for ; Mon, 5 Feb 2024 09:46:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3I0zyeuRiNsuu1/lcs7KY0trwCaVkfdzLPpHqQ/WUpE=; b=nQ498UUcx2cDcK eM5LgHTDb0Sw8Csfb2a6In0ZUeo0DtM0hWU7PGOjzSZbnoXLqaO5EQuqYnKe6GxtpAyGwmbmmWa5q cnIwvp5r2ZxDR5uxkmhBXzFevp/CSkRcwD7HxzSuMtVSoZXoV38cT2yRXS9OhxnE00VkTPH7Kp+eS xUymmVI7E4usQP/GUJgin0+FbuCDnSftyQBXQTRH3e+FHWu4KZ3+jxWMqj7+W7P6AnOwgVgGb3lQk D3Bi/2lUrdfbNu4PUU4mq0hbtsp+THc5u4CGBE/C1IdPJDygumpiIeNB0ZpJKlD9zW9+C564mrVd3 rpehibASjHhOo5QAqULw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rWvYW-00000002fn3-28XA; Mon, 05 Feb 2024 09:46:24 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rWvYT-00000002fm7-0SVn; Mon, 05 Feb 2024 09:46:22 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 65FAC60FD2; Mon, 5 Feb 2024 09:46:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AEA44C433C7; Mon, 5 Feb 2024 09:46:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1707126380; bh=S97KO5vp8gvf1SplDj/NGWxNDyP6qbms4ZkJbU5yooM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=bNRiIrQzbsUHuNnGrTyP97HsR6a5ElJ8g/yOEAUSEgMLXjrD1wrompGhpSa784aDm BOJIFakdCbJ0oLGWnXmjvko1iKXoIYs+tkYLq1ozX11wzikPpCorAkMLycbrZOjvfE 871aPrxCMtGwj9JCNpg8MCD/eVsBGYDb7chMM/moiMdAow6Dfks+AKxhryvwYjag+k gquq3s0gH9ZJRp9Qlr44GigOojab3TfuwWgk7mC8ZOhtow2GGRAOxoRh6V4RJCpfs6 rCI57Q7MPII5wAtiDPmoNej4WLo/WmuWTqRu1K5rFDS7wdbrexH1SexDwC10KXdOIG MtJ2paw/8y1YQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1rWvYO-000MhB-Iw; Mon, 05 Feb 2024 09:46:16 +0000 Date: Mon, 05 Feb 2024 09:46:16 +0000 Message-ID: <868r3z6y6v.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Kees Cook , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy , "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , Florian Weimer , Christian Brauner , Thiago Jung Bauermann , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v8 13/38] KVM: arm64: Manage GCS registers for guests In-Reply-To: <20240203-arm64-gcs-v8-13-c9fec77673ef@kernel.org> References: <20240203-arm64-gcs-v8-0-c9fec77673ef@kernel.org> <20240203-arm64-gcs-v8-13-c9fec77673ef@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org, corbet@lwn.net, akpm@linux-foundation.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, arnd@arndb.de, oleg@redhat.com, ebiederm@xmission.com, keescook@chromium.org, shuah@kernel.org, rick.p.edgecombe@intel.com, debug@rivosinc.com, ardb@kernel.org, Szabolcs.Nagy@arm.com, hjl.tools@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, fweimer@redhat.com, brauner@kernel.org, thiago.bauermann@linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240205_014621_260946_7C9BFC7F X-CRM114-Status: GOOD ( 32.37 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sat, 03 Feb 2024 12:25:39 +0000, Mark Brown wrote: > > GCS introduces a number of system registers for EL1 and EL0, on systems and EL2. > with GCS we need to context switch them and expose them to VMMs to allow > guests to use GCS, as well as describe their fine grained traps to > nested virtualisation. Traps are already disabled. The latter is not true with NV, since the guest is in control of the FGT registers. > > Signed-off-by: Mark Brown > --- > arch/arm64/include/asm/kvm_host.h | 12 ++++++++++++ > arch/arm64/kvm/emulate-nested.c | 4 ++++ > arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 17 +++++++++++++++++ > arch/arm64/kvm/sys_regs.c | 22 ++++++++++++++++++++++ > 4 files changed, 55 insertions(+) > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index 21c57b812569..6c7ea7f9cd92 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -388,6 +388,12 @@ enum vcpu_sysreg { > GCR_EL1, /* Tag Control Register */ > TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ > > + /* Guarded Control Stack registers */ > + GCSCRE0_EL1, /* Guarded Control Stack Control (EL0) */ > + GCSCR_EL1, /* Guarded Control Stack Control (EL1) */ This is subjected to VNCR (0x8D0). > + GCSPR_EL0, /* Guarded Control Stack Pointer (EL0) */ > + GCSPR_EL1, /* Guarded Control Stack Pointer (EL1) */ So is this one (0x8C0). And how about the *_EL2 versions? > + > /* 32bit specific registers. */ > DACR32_EL2, /* Domain Access Control Register */ > IFSR32_EL2, /* Instruction Fault Status Register */ > @@ -1221,6 +1227,12 @@ static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature) > > #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f)) > > +static inline bool has_gcs(void) > +{ > + return IS_ENABLED(CONFIG_ARM64_GCS) && > + cpus_have_final_cap(ARM64_HAS_GCS); > +} > + > int kvm_trng_call(struct kvm_vcpu *vcpu); > #ifdef CONFIG_KVM > extern phys_addr_t hyp_mem_base; > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > index 431fd429932d..24eb7eccbae4 100644 > --- a/arch/arm64/kvm/emulate-nested.c > +++ b/arch/arm64/kvm/emulate-nested.c > @@ -1098,8 +1098,12 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = { > SR_FGT(SYS_ESR_EL1, HFGxTR, ESR_EL1, 1), > SR_FGT(SYS_DCZID_EL0, HFGxTR, DCZID_EL0, 1), > SR_FGT(SYS_CTR_EL0, HFGxTR, CTR_EL0, 1), > + SR_FGT(SYS_GCSPR_EL0, HFGxTR, nGCS_EL0, 1), > SR_FGT(SYS_CSSELR_EL1, HFGxTR, CSSELR_EL1, 1), > SR_FGT(SYS_CPACR_EL1, HFGxTR, CPACR_EL1, 1), > + SR_FGT(SYS_GCSCR_EL1, HFGxTR, nGCS_EL1, 1), > + SR_FGT(SYS_GCSPR_EL1, HFGxTR, nGCS_EL1, 1), > + SR_FGT(SYS_GCSCRE0_EL1, HFGxTR, nGCS_EL0, 1), This is clearly wrong on all 4 counts (the n prefix gives it away...). > SR_FGT(SYS_CONTEXTIDR_EL1, HFGxTR, CONTEXTIDR_EL1, 1), > SR_FGT(SYS_CLIDR_EL1, HFGxTR, CLIDR_EL1, 1), > SR_FGT(SYS_CCSIDR_EL1, HFGxTR, CCSIDR_EL1, 1), > diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h > index bb6b571ec627..ec34d4a90717 100644 > --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h > +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h > @@ -25,6 +25,8 @@ static inline void __sysreg_save_user_state(struct kvm_cpu_context *ctxt) > { > ctxt_sys_reg(ctxt, TPIDR_EL0) = read_sysreg(tpidr_el0); > ctxt_sys_reg(ctxt, TPIDRRO_EL0) = read_sysreg(tpidrro_el0); > + if (has_gcs()) > + ctxt_sys_reg(ctxt, GCSPR_EL0) = read_sysreg_s(SYS_GCSPR_EL0); We have had this discussion in the past. This must be based on the VM's configuration. Guarding the check with the host capability is a valuable optimisation, but that's nowhere near enough. See the series that I have posted on this very subject (you're on Cc), but you are welcome to invent your own mechanism in the meantime. > } > > static inline bool ctxt_has_mte(struct kvm_cpu_context *ctxt) > @@ -62,6 +64,12 @@ static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) > ctxt_sys_reg(ctxt, PAR_EL1) = read_sysreg_par(); > ctxt_sys_reg(ctxt, TPIDR_EL1) = read_sysreg(tpidr_el1); > > + if (has_gcs()) { > + ctxt_sys_reg(ctxt, GCSPR_EL1) = read_sysreg_el1(SYS_GCSPR); > + ctxt_sys_reg(ctxt, GCSCR_EL1) = read_sysreg_el1(SYS_GCSCR); > + ctxt_sys_reg(ctxt, GCSCRE0_EL1) = read_sysreg_s(SYS_GCSCRE0_EL1); > + } > + Same thing. > if (ctxt_has_mte(ctxt)) { > ctxt_sys_reg(ctxt, TFSR_EL1) = read_sysreg_el1(SYS_TFSR); > ctxt_sys_reg(ctxt, TFSRE0_EL1) = read_sysreg_s(SYS_TFSRE0_EL1); > @@ -95,6 +103,8 @@ static inline void __sysreg_restore_user_state(struct kvm_cpu_context *ctxt) > { > write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0); > write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0); > + if (has_gcs()) > + write_sysreg_s(ctxt_sys_reg(ctxt, GCSPR_EL0), SYS_GCSPR_EL0); > } > > static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) > @@ -138,6 +148,13 @@ static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) > write_sysreg(ctxt_sys_reg(ctxt, PAR_EL1), par_el1); > write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL1), tpidr_el1); > > + if (has_gcs()) { > + write_sysreg_el1(ctxt_sys_reg(ctxt, GCSPR_EL1), SYS_GCSPR); > + write_sysreg_el1(ctxt_sys_reg(ctxt, GCSCR_EL1), SYS_GCSCR); > + write_sysreg_s(ctxt_sys_reg(ctxt, GCSCRE0_EL1), > + SYS_GCSCRE0_EL1); > + } > + For the benefit of the unsuspecting reviewers, and in the absence of a public specification (which the XML drop isn't), it would be good to have the commit message explaining the rationale of what gets saved when. > if (ctxt_has_mte(ctxt)) { > write_sysreg_el1(ctxt_sys_reg(ctxt, TFSR_EL1), SYS_TFSR); > write_sysreg_s(ctxt_sys_reg(ctxt, TFSRE0_EL1), SYS_TFSRE0_EL1); > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 30253bd19917..83ba767e75d2 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -2000,6 +2000,23 @@ static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, > .visibility = mte_visibility, \ > } > > +static unsigned int gcs_visibility(const struct kvm_vcpu *vcpu, > + const struct sys_reg_desc *rd) > +{ > + if (has_gcs()) > + return 0; Yet another case of exposing potentially unwanted state, to the VMM this time. > + > + return REG_HIDDEN; > +} > + > +#define GCS_REG(name) { \ > + SYS_DESC(SYS_##name), \ > + .access = undef_access, \ > + .reset = reset_unknown, \ > + .reg = name, \ > + .visibility = gcs_visibility, \ > +} > + > static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, > const struct sys_reg_desc *rd) > { > @@ -2376,6 +2393,10 @@ static const struct sys_reg_desc sys_reg_descs[] = { > PTRAUTH_KEY(APDB), > PTRAUTH_KEY(APGA), > > + GCS_REG(GCSCR_EL1), > + GCS_REG(GCSPR_EL1), > + GCS_REG(GCSCRE0_EL1), > + > { SYS_DESC(SYS_SPSR_EL1), access_spsr}, > { SYS_DESC(SYS_ELR_EL1), access_elr}, > > @@ -2462,6 +2483,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { > { SYS_DESC(SYS_SMIDR_EL1), undef_access }, > { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, > { SYS_DESC(SYS_CTR_EL0), access_ctr }, > + GCS_REG(GCSPR_EL0), > { SYS_DESC(SYS_SVCR), undef_access }, > > { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, > Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv