From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87105C433FE for ; Wed, 30 Nov 2022 14:48:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2Aq4J2Z85p3+pZtxtHOkmLozHnrAWtvbwNtma5lXg5w=; b=mgw23GBB6u9UZG QNDTgLjCNVg0Sd6H+QIsJIIv3uPJ4zK1hbh2h/6ffEySWS6HJATt590dXqyJ4RMHa7w41Urp+blcI qY/jJbB6FhBbPLxcuNeFAp32Oz5JUg/PZgBl6z/vbmi+OTs2hgd17sv4ObiQUHtkqlJPtFL8fSlrI ELgua9A8JSeHinNBrQ3Zp5w49v6Z+89Wvkj93jsDtXy94VLOtRyIwPLYR+DT9sN59J2+d1Ead1xxv AsPuMx+jbhOjLUe3rF7b4ZUD6F2pcssVso+8ypLPkfAE9/NDijn1yLb9DmHBXSct8jogIB8i/BfZN rcUXV1H9fkthKkj96M1g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0ONW-00H3Vc-U2; Wed, 30 Nov 2022 14:48:02 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0ONU-00H3U8-1p for linux-riscv@lists.infradead.org; Wed, 30 Nov 2022 14:48:01 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C622761C39; Wed, 30 Nov 2022 14:47:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3557EC433D6; Wed, 30 Nov 2022 14:47:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1669819678; bh=BW3glwJdAgcquisZ858SN49s35yyYqpIA+9FpdjY5iM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ALxY+CFYvAbplLO+Hx/N4O3NpzbvaySvk0nfAT4kVUupPtk8eiIJEPauPSRiKSQYQ jaEuk3EQLF7HMDsTLopSF/oBX0cD0uebGk6BERbAQRvCQBVyuguvV0yeCzr9KfHjYs h6ZIWPf+1uJ6M5GpIRIHtPCODP2CxLD4vg0xAucrg0jwvJKz/SUOxsyllejrWpHkE0 Lw1/lk8/UqU2nETjhIp7rghqczNwpgCxVw2uOWK8+ps5NivouB7uph1TlyA7hD+9MZ rPO59hBKCZYd8624e85H14YKrtM3oU/BQPxLKWRc416Vv+xzLGoreojgr2Gxmf68qu 4M81D54/BGyfw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1p0ONP-009bnX-Qd; Wed, 30 Nov 2022 14:47:56 +0000 Date: Wed, 30 Nov 2022 14:47:55 +0000 Message-ID: <86cz94mrc4.wl-maz@kernel.org> From: Marc Zyngier To: Anup Patel Cc: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Daniel Lezcano , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v13 3/7] genirq: Add mechanism to multiplex a single HW IPI In-Reply-To: <20221129142449.886518-4-apatel@ventanamicro.com> References: <20221129142449.886518-1-apatel@ventanamicro.com> <20221129142449.886518-4-apatel@ventanamicro.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: apatel@ventanamicro.com, palmer@dabbelt.com, paul.walmsley@sifive.com, tglx@linutronix.de, daniel.lezcano@linaro.org, atishp@atishpatra.org, Alistair.Francis@wdc.com, anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221130_064800_214832_EEBF99C0 X-CRM114-Status: GOOD ( 23.58 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, 29 Nov 2022 14:24:45 +0000, Anup Patel wrote: > > All RISC-V platforms have a single HW IPI provided by the INTC local > interrupt controller. The HW method to trigger INTC IPI can be through > external irqchip (e.g. RISC-V AIA), through platform specific device > (e.g. SiFive CLINT timer), or through firmware (e.g. SBI IPI call). > > To support multiple IPIs on RISC-V, we add a generic IPI multiplexing > mechanism which help us create multiple virtual IPIs using a single > HW IPI. This generic IPI multiplexing is inspired from the Apple AIC > irqchip driver and it is shared by various RISC-V irqchip drivers. > > Signed-off-by: Anup Patel > --- > include/linux/irq.h | 3 + > kernel/irq/Kconfig | 5 ++ > kernel/irq/Makefile | 1 + > kernel/irq/ipi-mux.c | 193 +++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 202 insertions(+) > create mode 100644 kernel/irq/ipi-mux.c [...] This is finally starting to look acceptable. My only changes are: diff --git a/kernel/irq/ipi-mux.c b/kernel/irq/ipi-mux.c index 626c564233e9..1a6ba19b736c 100644 --- a/kernel/irq/ipi-mux.c +++ b/kernel/irq/ipi-mux.c @@ -69,6 +69,12 @@ static void ipi_mux_send_mask(struct irq_data *d, const struct cpumask *mask) */ smp_mb__after_atomic(); + /* + * The flag writes must complete before the physical IPI is + * issued to another CPU. This is implied by the control + * dependency on the result of atomic_read() below, which is + * itself already ordered after the vIPI flag write. + */ if (!(pending & ibit) && (atomic_read(&icpu->enable) & ibit)) ipi_mux_send(cpu); } @@ -160,7 +166,7 @@ int ipi_mux_create(unsigned int nr_ipi, void (*mux_send)(unsigned int cpu)) goto fail_free_cpu; } - domain = irq_domain_create_simple(fwnode, nr_ipi, 0, + domain = irq_domain_create_linear(fwnode, nr_ipi, &ipi_mux_domain_ops, NULL); if (!domain) { pr_err("unable to add IPI Mux domain\n"); The first hunk preserve an important piece of information about how delicate the ordering is, while the second only allocates the irqdesc structures as needed, not upfront. I'll shortly go over the rest of the irqchip code and can apply the above myself if there is nothing more to fix. I've also converted the AIC driver over to this[1], and nothing broke so far... M. [1] https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=irq/ipi-mux -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv