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From: Marc Zyngier <maz@kernel.org>
To: Icenowy Zheng <uwu@icenowy.me>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Samuel Holland <samuel@sholland.org>,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH] irqchip/sifive-plic: drop quirk for two-cell variant
Date: Wed, 23 Nov 2022 13:13:52 +0000	[thread overview]
Message-ID: <86ilj5oltb.wl-maz@kernel.org> (raw)
In-Reply-To: <16d01eebc1693916fc74e1e75458d6c0f080cf37.camel@icenowy.me>

On Wed, 23 Nov 2022 12:38:56 +0000,
Icenowy Zheng <uwu@icenowy.me> wrote:
> 
> 在 2022-11-22星期二的 17:28 +0000,Marc Zyngier写道:
> > On Mon, 21 Nov 2022 04:20:26 +0000,
> > Icenowy Zheng <uwu@icenowy.me> wrote:
> > > 
> > > As the special handling of edge-triggered interrupts are defined in
> > > the
> > > PLIC spec, we can assume it's not a quirk, but a feature of the
> > > PLIC
> > > spec; thus making it a quirk and use quirk-based codepath is not so
> > > necessary.
> > 
> > It *is* necessary.
> > 
> > > 
> > > Move to a #interrupt-cells-based practice which will allow both
> > > device
> > > trees without interrupt flags and with interrupt flags work for all
> > > compatible strings.
> > 
> > No. You're tying together two unrelated concepts:
> > 
> > - Edges get dropped in some implementations (and only some). You can
> >   argue that the architecture allows it, but I see it is an
> >   implementation bug.
> 
> As the specification allows it, it's not an implementation bug -- and
> for those which do not show this problem, it's possible that it's just
> all using the same trigger type (e.g. Rocket).

What are you against? The fact that this is flagged as a quirk?
Honestly, I don't care about that. If we can fold all implementations
into the same scheme, that's fine by me.

> 
> > 
> > - The need for expressing additional information in the interrupt
> >   specifier is not necessarily related to the above. Other interrupt
> >   controllers use extra cells to encode the interrupt affinity, for
> >   example.
> 
> I think in these situations, if the interrupt controller does not
> contain any special handling for edge interrupts, we can just describe
> them as level ones in SW.

No, that's utterly wrong. We don't describe an edge as level. Ever.

> 
> > 
> > I want these two things to be kept separate. Otherwise, once we get
> > some fancy ACPI support for RISCV (no, please...), we'll have to redo
> > the whole thing...
> > 
> > > In addition, this addresses a stable version DT binding violation -
> > > -
> > > Linux v5.19 comes with "thead,c900-plic" with #interrupt-cells
> > > defined to
> > > be 1 instead of 2, this commit will allow DTs that complies to
> > > Linux
> > > v5.19 binding work (although no such DT is devliered to the public
> > > now).
> > 
> > *That* is what should get fixed.
> 
> Supporting all stable versions' DT binding is our promise, I think.

Absolutely. And I'm asking you to fix it. And only that.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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  reply	other threads:[~2022-11-23 13:30 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-21  4:20 [PATCH] irqchip/sifive-plic: drop quirk for two-cell variant Icenowy Zheng
2022-11-22 17:28 ` Marc Zyngier
2022-11-23 12:38   ` Icenowy Zheng
2022-11-23 13:13     ` Marc Zyngier [this message]
2022-11-23 13:16       ` Icenowy Zheng
2022-11-23 13:31         ` Marc Zyngier
2022-11-23 13:35           ` Icenowy Zheng
2022-11-23 14:07             ` Marc Zyngier

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