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Thu, 23 Jan 2025 12:12:04 +0000 Date: Thu, 23 Jan 2025 12:12:03 +0000 Message-ID: <86msfhviek.wl-maz@kernel.org> From: Marc Zyngier To: Manivannan Sadhasivam Cc: Chen Wang , Chen Wang , kw@linux.com, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, bhelgaas@google.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, lee@kernel.org, lpieralisi@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, pbrobinson@gmail.com, robh@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com, helgaas@kernel.org Subject: Re: [PATCH v3 2/5] PCI: sg2042: Add Sophgo SG2042 PCIe driver In-Reply-To: <20250122173451.5c7pdchnyee7iy6t@thinkpad> References: <20250119122353.v3tzitthmu5tu3dg@thinkpad> <20250122173451.5c7pdchnyee7iy6t@thinkpad> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: manivannan.sadhasivam@linaro.org, unicorn_wang@outlook.com, unicornxw@gmail.com, kw@linux.com, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, bhelgaas@google.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, lee@kernel.org, lpieralisi@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, pbrobinson@gmail.com, robh@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com, helgaas@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250123_041208_686082_1A6B1758 X-CRM114-Status: GOOD ( 21.64 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, 22 Jan 2025 17:34:51 +0000, Manivannan Sadhasivam wrote: > > + Marc (for the IRQCHIP implementation review) > > On Wed, Jan 22, 2025 at 09:28:12PM +0800, Chen Wang wrote: > > > > > > +static int sg2042_pcie_setup_msi(struct sg2042_pcie *pcie, > > > > + struct device_node *msi_node) > > > > +{ > > > > + struct device *dev = pcie->cdns_pcie->dev; > > > > + struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); > > > > + struct irq_domain *parent_domain; > > > > + int ret = 0; > > > > + > > > > + if (!of_property_read_bool(msi_node, "msi-controller")) > > > > + return -ENODEV; > > > > + > > > > + ret = of_irq_get_byname(msi_node, "msi"); > > > > + if (ret <= 0) { > > > > + dev_err(dev, "%pOF: failed to get MSI irq\n", msi_node); > > > > + return ret; > > > > + } > > > > + pcie->msi_irq = ret; > > > > + > > > > + irq_set_chained_handler_and_data(pcie->msi_irq, > > > > + sg2042_pcie_msi_chained_isr, pcie); > > > > + > > > > + parent_domain = irq_domain_create_linear(fwnode, MSI_DEF_NUM_VECTORS, > > > > + &sg2042_pcie_msi_domain_ops, pcie); > > > > + if (!parent_domain) { > > > > + dev_err(dev, "%pfw: Failed to create IRQ domain\n", fwnode); > > > > + return -ENOMEM; > > > > + } > > > > + irq_domain_update_bus_token(parent_domain, DOMAIN_BUS_NEXUS); > > > > + > > > The MSI controller is wired to PLIC isn't it? If so, why can't you use > > > hierarchial MSI domain implementation as like other controller drivers? > > > > The method used here is somewhat similar to dw_pcie_allocate_domains() in > > drivers/pci/controller/dwc/pcie-designware-host.c. This MSI controller is > > about Method A, the PCIe controller implements an MSI interrupt controller > > inside, and connect to PLIC upward through only ONE interrupt line. Because > > MSI to PLIC is multiple to one, I use linear mode here and use chained ISR > > to handle the interrupts. > > > > Hmm, ok. I'm not an IRQCHIP expert, but I'll defer to Marc to review the IRQCHIP > implementation part. I don't offer this service anymore, I'm afraid. As for the "I create my own non-hierarchical IRQ domain", this is something that happens for all completely mis-designed interrupt controllers, MSI or not, that multiplex interrupts. These implementations are stuck in the previous century, and seeing this on modern designs, for a "server SoC", is really pathetic. maybe you now understand why I don't offer this sort of reviewing service anymore. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv