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From: Thomas Gleixner <tglx@linutronix.de>
To: Anup Patel <apatel@ventanamicro.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Frank Rowand <frowand.list@gmail.com>,
	Conor Dooley <conor+dt@kernel.org>
Cc: "Anup Patel" <apatel@ventanamicro.com>,
	devicetree@vger.kernel.org,
	"Saravana Kannan" <saravanak@google.com>,
	"Marc Zyngier" <maz@kernel.org>,
	"Anup Patel" <anup@brainfault.org>,
	linux-kernel@vger.kernel.org, "Björn Töpel" <bjorn@kernel.org>,
	"Atish Patra" <atishp@atishpatra.org>,
	linux-riscv@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	"Andrew Jones" <ajones@ventanamicro.com>
Subject: Re: [PATCH v12 23/25] irqchip/riscv-aplic: Add support for MSI-mode
Date: Fri, 16 Feb 2024 22:04:03 +0100	[thread overview]
Message-ID: <8734tsce9o.ffs@tglx> (raw)
In-Reply-To: <20240127161753.114685-24-apatel@ventanamicro.com>

On Sat, Jan 27 2024 at 21:47, Anup Patel wrote:
> We extend the existing APLIC irqchip driver to support MSI-mode for
> RISC-V platforms having both wired interrupts and MSIs.

We? Just s/We//

> +
> +static void aplic_msi_irq_unmask(struct irq_data *d)
> +{
> +	aplic_irq_unmask(d);
> +	irq_chip_unmask_parent(d);
> +}
> +
> +static void aplic_msi_irq_mask(struct irq_data *d)
> +{
> +	aplic_irq_mask(d);
> +	irq_chip_mask_parent(d);
> +}

Again asymmetric vs. unmask()

> +static void aplic_msi_irq_eoi(struct irq_data *d)
> +{
> +	struct aplic_priv *priv = irq_data_get_irq_chip_data(d);
> +	u32 reg_off, reg_mask;
> +
> +	/*
> +	 * EOI handling only required only for level-triggered
> +	 * interrupts in APLIC MSI mode.
> +	 */
> +
> +	reg_off = APLIC_CLRIP_BASE + ((d->hwirq / APLIC_IRQBITS_PER_REG) * 4);
> +	reg_mask = BIT(d->hwirq % APLIC_IRQBITS_PER_REG);
> +	switch (irqd_get_trigger_type(d)) {
> +	case IRQ_TYPE_LEVEL_LOW:
> +		if (!(readl(priv->regs + reg_off) & reg_mask))
> +			writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE);

A comment what this condition is for would be nice.

Thanks,

        tglx

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  reply	other threads:[~2024-02-16 21:04 UTC|newest]

Thread overview: 86+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-27 16:17 [PATCH v12 00/25] Linux RISC-V AIA Support Anup Patel
2024-01-27 16:17 ` [PATCH v12 01/25] irqchip/gic-v3: Make gic_irq_domain_select() robust for zero parameter count Anup Patel
2024-02-15 11:47   ` Marc Zyngier
2024-01-27 16:17 ` [PATCH v12 02/25] genirq/irqdomain: Remove the param count restriction from select() Anup Patel
2024-02-22 13:01   ` Aishwarya TCV
2024-02-22 16:28     ` Marc Zyngier
2024-02-22 22:59       ` Aishwarya TCV
     [not found]   ` <CGME20240223102258eucas1p119f38e40f769c883c0a502e9e26be888@eucas1p1.samsung.com>
2024-02-23 10:22     ` Marek Szyprowski
2024-02-23 10:45       ` Biju Das
2024-02-23 10:56         ` Marek Szyprowski
2024-02-23 11:01           ` Biju Das
2024-01-27 16:17 ` [PATCH v12 03/25] genirq/msi: Extend msi_parent_ops Anup Patel
2024-01-27 16:17 ` [PATCH v12 04/25] genirq/irqdomain: Add DOMAIN_BUS_DEVICE_IMS Anup Patel
2024-02-15 11:54   ` Marc Zyngier
2024-02-15 15:01     ` Thomas Gleixner
2024-01-27 16:17 ` [PATCH v12 05/25] platform-msi: Prepare for real per device domains Anup Patel
2024-01-27 16:17 ` [PATCH v12 06/25] irqchip: Convert all platform MSI users to the new API Anup Patel
2024-01-27 16:17 ` [PATCH v12 07/25] genirq/msi: Provide optional translation op Anup Patel
2024-01-27 16:17 ` [PATCH v12 08/25] genirq/msi: Split msi_domain_alloc_irq_at() Anup Patel
2024-01-27 16:17 ` [PATCH v12 09/25] genirq/msi: Provide DOMAIN_BUS_WIRED_TO_MSI Anup Patel
2024-01-27 16:17 ` [PATCH v12 10/25] genirq/msi: Optionally use dev->fwnode for device domain Anup Patel
2024-01-27 16:17 ` [PATCH v12 11/25] genirq/msi: Provide allocation/free functions for "wired" MSI interrupts Anup Patel
2024-01-27 16:17 ` [PATCH v12 12/25] genirq/irqdomain: Reroute device MSI create_mapping Anup Patel
2024-01-27 16:17 ` [PATCH v12 13/25] genirq/msi: Provide MSI_FLAG_PARENT_PM_DEV Anup Patel
2024-01-27 16:17 ` [PATCH v12 14/25] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2024-02-16 15:33   ` Thomas Gleixner
2024-02-16 17:11     ` Anup Patel
2024-02-16 20:22       ` Thomas Gleixner
2024-02-17  5:42         ` Anup Patel
2024-01-27 16:17 ` [PATCH v12 15/25] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2024-01-27 16:17 ` [PATCH v12 16/25] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2024-01-27 16:17 ` [PATCH v12 17/25] genirq/matrix: Dynamic bitmap allocation Anup Patel
2024-01-27 16:17 ` [PATCH v12 18/25] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2024-02-07  9:43   ` Björn Töpel
2024-02-16 18:40   ` Thomas Gleixner
2024-02-18 13:16     ` Anup Patel
2024-01-27 16:17 ` [PATCH v12 19/25] irqchip/riscv-imsic: Add device MSI domain support for platform devices Anup Patel
2024-02-06 15:36   ` Björn Töpel
2024-02-16 20:12   ` Thomas Gleixner
2024-02-19  4:10     ` Anup Patel
2024-01-27 16:17 ` [PATCH v12 20/25] irqchip/riscv-imsic: Add device MSI domain support for PCI devices Anup Patel
2024-02-16 20:14   ` Thomas Gleixner
2024-02-19  4:41     ` Anup Patel
2024-01-27 16:17 ` [PATCH v12 21/25] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2024-01-27 16:17 ` [PATCH v12 22/25] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2024-02-01  6:39   ` Andy Chiu
2024-02-19 10:28     ` Anup Patel
2024-02-02  9:29   ` Clément Léger
2024-02-02 10:30     ` Anup Patel
2024-02-02 10:33       ` Clément Léger
2024-02-16 20:50   ` Thomas Gleixner
2024-02-19  9:35     ` Anup Patel
2024-01-27 16:17 ` [PATCH v12 23/25] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2024-02-16 21:04   ` Thomas Gleixner [this message]
2024-02-19  9:45     ` Anup Patel
2024-01-27 16:17 ` [PATCH v12 24/25] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2024-01-27 16:17 ` [PATCH v12 25/25] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2024-01-27 16:20 ` [PATCH v12 00/25] Linux RISC-V AIA Support Anup Patel
2024-02-14 19:54   ` Thomas Gleixner
2024-02-15  5:48     ` Anup Patel
2024-02-15 19:59       ` Thomas Gleixner
2024-02-16 21:05         ` Thomas Gleixner
2024-02-20  6:12           ` Anup Patel
2024-02-15 11:57     ` Marc Zyngier
2024-01-30  7:16 ` Björn Töpel
2024-01-30  7:52   ` Björn Töpel
2024-01-30 10:02     ` Anup Patel
2024-01-30 11:05       ` Björn Töpel
2024-01-30 10:23     ` Anup Patel
2024-01-30 11:46       ` Björn Töpel
2024-01-30 14:48         ` Björn Töpel
2024-01-30 15:19           ` Anup Patel
2024-01-30 15:48           ` Anup Patel
2024-01-30 17:49             ` Björn Töpel
2024-02-01 15:07               ` Anup Patel
2024-02-01 18:45                 ` Björn Töpel
2024-02-06 15:39 ` Björn Töpel
2024-02-06 17:39   ` Anup Patel
2024-02-07  7:27     ` Björn Töpel
2024-02-07  9:18       ` Anup Patel
2024-02-07  9:37         ` Björn Töpel
2024-02-07 12:55           ` Björn Töpel
2024-02-07 13:08             ` Anup Patel
2024-02-07 13:10             ` Anup Patel
2024-02-08 10:10 ` Andrea Parri
2024-02-16 11:33   ` Anup Patel

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