From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1200C433EF for ; Tue, 19 Oct 2021 10:18:36 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 690CE6137E for ; Tue, 19 Oct 2021 10:18:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 690CE6137E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=A5BETi50A9/4tMCjFqeZatVGBLBvqor7sXD7F5OyvBE=; b=ztc0o3w/JHGmJ7 qMM72VRkjgyZYZeHFFRzeodut/i6/MsxFO0MFtVGYMG7fwAyr0e80GCdWy+bKWIqnCXVpJGU40j3+ TOdveTMk5Bxa0GNC4hms0VFg5aHQx+t9xHPi9gd9P5dNvItNCefzzb4fNl2+FOq78gPLRMR2WVOTa a5QNTY9OTZuAmIU6nFh9Zn4/pJdFLk/cF7geCWQLbgrWi+pHz36JsN52rTK2gYsPt4tsk1bAp437a 9Z97UQbcRBuZ9ubms9JO0xSBMsUBDmaHz5WIaPFyPc/siRE70mBYEOC4KIKFzU5vgeXXdt0PtGIAy 8DX76nzsA48bLfctJY5w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mcmCR-000n7Z-MJ; Tue, 19 Oct 2021 10:18:27 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mcmCE-000n3Z-AE for linux-riscv@lists.infradead.org; Tue, 19 Oct 2021 10:18:15 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id EF18B6137D; Tue, 19 Oct 2021 10:18:13 +0000 (UTC) Received: from ip-185-104-136-29.ptr.icomera.net ([185.104.136.29] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mcmCB-000AqP-Mb; Tue, 19 Oct 2021 11:18:11 +0100 Date: Tue, 19 Oct 2021 11:18:09 +0100 Message-ID: <8735oxuxlq.wl-maz@kernel.org> From: Marc Zyngier To: Guo Ren Cc: Samuel Holland , Anup Patel , Atish Patra , Thomas Gleixner , Palmer Dabbelt , Heiko =?UTF-8?B?U3TDvGJuZXI=?= , Rob Herring , Linux Kernel Mailing List , linux-riscv , Guo Ren Subject: Re: [PATCH V4 1/3] irqchip/sifive-plic: Add thead,c900-plic support In-Reply-To: References: <20211016032200.2869998-1-guoren@kernel.org> <20211016032200.2869998-2-guoren@kernel.org> <8be1bdbd-365d-cd28-79d7-b924908f9e39@sholland.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.104.136.29 X-SA-Exim-Rcpt-To: guoren@kernel.org, samuel@sholland.org, anup@brainfault.org, atish.patra@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de, robh@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, guoren@linux.alibaba.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211019_031814_416303_1FC36743 X-CRM114-Status: GOOD ( 25.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, 19 Oct 2021 10:33:49 +0100, Guo Ren wrote: > > If you have an 'automask' behavior and yet the HW doesn't record this > > in a separate bit, then you need to track this by yourself in the > > irq_eoi() callback instead. I guess that you would skip the write to > > the CLAIM register in this case, though I have no idea whether this > > breaks > > the HW interrupt state or not. > The problem is when enable bit is 0 for that irq_number, > "writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM)" wouldn't affect > the hw state machine. Then this irq would enter in ack state and no > continues irqs could come in. Really? This means that you cannot mask an interrupt while it is being handled? How great... > > > > There is an example of this in the Apple AIC driver. > Thx for the tip, I think your suggestion is: > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -163,7 +163,12 @@ static void plic_irq_eoi(struct irq_data *d) > { > struct plic_handler *handler = this_cpu_ptr(&plic_handlers); > > - writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > + if (irqd_irq_masked(d)) { > + plic_irq_unmask(d); > + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > + plic_irq_mask(d); This looks pretty dodgy. You are relying on interrupts being globally masked on the CPU, I guess. It probably works today, but man, what a terrible HW implementation. You'll definitely have to move this into a c900-specific callback. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv