From: Eric Cheng <eric.cheng.linux@gmail.com>
To: Anup Patel <apatel@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: devicetree@vger.kernel.org,
"Saravana Kannan" <saravanak@google.com>,
"Marc Zyngier" <maz@kernel.org>,
"Anup Patel" <anup@brainfault.org>,
linux-kernel@vger.kernel.org, "Björn Töpel" <bjorn@kernel.org>,
"Atish Patra" <atishp@atishpatra.org>,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
"Andrew Jones" <ajones@ventanamicro.com>
Subject: Re: [PATCH v16 2/9] irqchip: Add RISC-V incoming MSI controller early driver
Date: Fri, 19 Apr 2024 11:23:20 +0800 [thread overview]
Message-ID: <8738cb85-fac1-4a15-9666-eb05316f5368@gmail.com> (raw)
In-Reply-To: <20240307140307.646078-3-apatel@ventanamicro.com>
On 3/7/2024 10:03 PM, Anup Patel wrote:
> +static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode,
> + struct imsic_global_config *global,
> + u32 *nr_parent_irqs,
> + u32 *nr_mmios)
> +{
...
> + /*
> + * Find first bit position of group index.
> + * If not specified assumed the default APLIC-IMSIC configuration.
> + */
> + rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift",
> + &global->group_index_shift);
> + if (rc)
> + global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2;
> +
> + /* Find number of interrupt identities */
> + rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-ids",
> + &global->nr_ids);
Will here check if the pass-in interrupt identity number is (multi-64 -1) &&
between [63, 2047]?
Per spec AIA v1.0, Sec. 3.1 Interrupt files and interrupt identities:
"The number of interrupt identities supported by an interrupt file (and hence
the number of active
bits in each array) is one less than a multiple of 64, and may be a minimum of
63 and a maximum
of 2047."
> + if (rc) {
> + pr_err("%pfwP: number of interrupt identities not found\n", fwnode);
> + return rc;
> + }
> +
...
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next prev parent reply other threads:[~2024-04-19 3:24 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-07 14:02 [PATCH v16 0/9] Linux RISC-V AIA Support Anup Patel
2024-03-07 14:02 ` [PATCH v16 1/9] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2024-03-07 14:03 ` [PATCH v16 2/9] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2024-04-19 3:23 ` Eric Cheng [this message]
2024-04-19 3:44 ` Anup Patel
2024-04-19 3:55 ` Eric Cheng
2024-03-07 14:03 ` [PATCH v16 3/9] irqchip/riscv-imsic: Add device MSI domain support for platform devices Anup Patel
2024-03-07 14:03 ` [PATCH v16 4/9] irqchip/riscv-imsic: Add device MSI domain support for PCI devices Anup Patel
2024-03-07 14:03 ` [PATCH v16 5/9] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2024-03-07 14:03 ` [PATCH v16 6/9] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2025-11-20 14:43 ` niliqiang
2025-11-21 8:50 ` Sunil V L
2025-11-21 13:54 ` niliqiang
2025-11-22 9:37 ` Marc Zyngier
2025-11-25 16:07 ` niliqiang
2025-11-25 16:42 ` Thomas Gleixner
2025-11-26 16:15 ` niliqiang
2024-03-07 14:03 ` [PATCH v16 7/9] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2024-03-07 14:03 ` [PATCH v16 8/9] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2024-03-07 14:03 ` [PATCH v16 9/9] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2024-03-07 14:11 ` [PATCH v16 0/9] Linux RISC-V AIA Support Anup Patel
2024-03-07 21:03 ` Thomas Gleixner
2024-03-08 11:11 ` Björn Töpel
2024-03-08 11:13 ` Björn Töpel
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