From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8280CC433EF for ; Wed, 20 Oct 2021 13:34:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5004C611C7 for ; Wed, 20 Oct 2021 13:34:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5004C611C7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+XWFUuxHuqpbgNzgj+dElB1ZSdBDfw0Te761clFpLio=; b=KpwiMgKp3iwBZZ VZh/H+4SfRxoYeoHyXHadpcZTLe/0JZgfEIarZVVEg5N0XdYwSS4T7vMSJSDdNEn5TqvYm0jfNzRf ap3YyRWRAktEOeeaTYe3V+xO0EuwAmIMtwvAQz+iQC2l26pib7XoV+8Gm9F/i4rjO/dHCp0KTgYz1 da3HhdGLrGQ6xfuC8G8cs9ThWy8vm58nfy7IpL2V5YOblFMRIikmLZodb4hrEoC9n8DeBOOL/0FOW IumuWfdJvWLj4jamKpEqooLJovsSwvLw/yaM5LtREmkDG6sRj56FrbJsiyLVkgFSlR1Ttf7P35Gju Tuqphs2L+3HWpiUsE6+Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdBjP-004cZA-85; Wed, 20 Oct 2021 13:34:11 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdBjM-004cY7-0r for linux-riscv@lists.infradead.org; Wed, 20 Oct 2021 13:34:09 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 99234611C6; Wed, 20 Oct 2021 13:34:07 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mdBjJ-000RVA-Hw; Wed, 20 Oct 2021 14:34:05 +0100 Date: Wed, 20 Oct 2021 14:34:05 +0100 Message-ID: <875ytrddma.wl-maz@kernel.org> From: Marc Zyngier To: Guo Ren Cc: Samuel Holland , Anup Patel , Atish Patra , Thomas Gleixner , Palmer Dabbelt , Heiko =?UTF-8?B?U3TDvGJuZXI=?= , Rob Herring , Linux Kernel Mailing List , linux-riscv , Guo Ren Subject: Re: [PATCH V4 1/3] irqchip/sifive-plic: Add thead,c900-plic support In-Reply-To: References: <20211016032200.2869998-1-guoren@kernel.org> <20211016032200.2869998-2-guoren@kernel.org> <8be1bdbd-365d-cd28-79d7-b924908f9e39@sholland.org> <8735oxuxlq.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: guoren@kernel.org, samuel@sholland.org, anup@brainfault.org, atish.patra@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de, robh@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, guoren@linux.alibaba.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_063408_107792_D917E7DE X-CRM114-Status: GOOD ( 26.77 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, 19 Oct 2021 14:27:02 +0100, Guo Ren wrote: > > On Tue, Oct 19, 2021 at 6:18 PM Marc Zyngier wrote: > > > > On Tue, 19 Oct 2021 10:33:49 +0100, > > Guo Ren wrote: > > > > > > If you have an 'automask' behavior and yet the HW doesn't record this > > > > in a separate bit, then you need to track this by yourself in the > > > > irq_eoi() callback instead. I guess that you would skip the write to > > > > the CLAIM register in this case, though I have no idea whether this > > > > breaks > > > > the HW interrupt state or not. > > > The problem is when enable bit is 0 for that irq_number, > > > "writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM)" wouldn't affect > > > the hw state machine. Then this irq would enter in ack state and no > > > continues irqs could come in. > > > > Really? This means that you cannot mask an interrupt while it is being > > handled? How great... > If the completion ID does not match an interrupt source that is > currently enabled for the target, the completion is silently ignored. > So, C9xx completion depends on enable-bit. Is that what the PLIC spec says? Or what your implementation does? I can understand that one implementation would be broken, but if the PLIC architecture itself is broken, that's far more concerning. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv