From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6637C56208 for ; Thu, 6 Aug 2026 14:45:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:References :In-Reply-To:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Q5JAb3FBVa1Ieq6tQ4ZKLlkSjFsOSZdyzyH6RN1O3OM=; b=gwQ4dtTB2wQNFB cNPrgm8sito2RJ56ihttbO5jRm31CpsHmO91rM1CwbSgJ1V//nwt8fyUwdtdyhu5uNXrO+PfjLY4U hjPqreoHuaEeh7HVJy2o3oDjST1xdYNNYbFTF4vECF0a99UymbG32jFiSdZA4WFAC09usWu3OoRwA ZHdI3Za8OXWTwtVH+7Pk5I3sLW+UkhAVcmCsbIzf5NDQ9jss3tXS/bsaYqMH4F8poRmNLZmARDugh PjXqeY5rTZAHJQ5r9fKLG2ZJgogm+iBQx6oP9WJq6EjONfsaue31Q8V26IibvvywSMyFRR2WLToKp jJBY7sDAiPM9Bxy0RROA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wrzLb-000000061KK-22Rc; Thu, 06 Aug 2026 14:45:27 +0000 Received: from galois.linutronix.de ([193.142.43.55]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wrzLW-000000061IV-0ukY; Thu, 06 Aug 2026 14:45:23 +0000 From: Nam Cao DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1786027515; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=V4IJ9dPDD7ujYacDqxd6wmTgSCWh3iQS9y0EGvh2GbM=; b=vvnHQqf3CT+6tyZkkqRjo305rMXFVOTYizwgBBjon871om9RhAeTKor7f16ybGiZ+IBB18 j//jk43lis2FapI6XrbVQiTUneINt+CSUdeWA79iRIx7nohBHfl0oXGS3ZeUfF/fBET5t5 ZV0pNtHwdGa1yUKt0p8occEA4Z7lrFoMVGCCLYUfm8/U+etH/UX6LdIjuPxAaBG5iN4PZi /vlQO6/szB68C/PhNXoOkmXve5oReOzuCWNWQYRKKmqkasuj7sSwsOZBt5QYya8PclYhCE FGQwlwqC07R0oO8lnDGKRlmnui8EKc7pws+AfZvngZTeRkUuKYTH1QM7pFLcYg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1786027515; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=V4IJ9dPDD7ujYacDqxd6wmTgSCWh3iQS9y0EGvh2GbM=; b=AcpzuNgtrbHDTMJgMUKgJzmAcIDRwIgOVNK+kvTRFlFG7yIbIfSnNmqR4eeucGYkSFmgKw 05ykDSXTKOFICLBQ== To: Charlie Jenkins , Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Conor Dooley , Paolo Bonzini , Andrew Morton , Shuah Khan , Radim =?utf-8?B?S3LEjW3DocWZ?= , Jesse Taube Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Charlie Jenkins Subject: Re: [PATCH v3 08/17] riscv: Use generated instruction headers for misaligned loads/stores In-Reply-To: <20260707-riscv_insn_table-v3-8-3f8e5f75ba97@gmail.com> References: <20260707-riscv_insn_table-v3-0-3f8e5f75ba97@gmail.com> <20260707-riscv_insn_table-v3-8-3f8e5f75ba97@gmail.com> Date: Thu, 06 Aug 2026 16:45:14 +0200 Message-ID: <87a4qzcnph.fsf@yellow.woof> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260806_074522_403178_9C8C2CDE X-CRM114-Status: UNSURE ( 8.32 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Charlie Jenkins writes: > -static int handle_scalar_misaligned_load(struct pt_regs *regs) > +static noinline int handle_scalar_misaligned_load(struct pt_regs *regs) Why noinline? I heard that compilers are usually better than human at deciding which functions to inline. > + if (rd) { > + if (!fp) > + *(unsigned long *)((unsigned long *)regs + rd) = (val.data_ulong << shift) >> shift; > + else if (len == 8) > + set_f64_rd(rd, regs, val.data_u64); > + else > + set_f32_rd(rd, regs, val.data_ulong); Why if (rd) condition? What if the instruction is loading to f0? > + rd = (8 + riscv_insn_c_sh_extract_xs2(insn)); Having to remember when to +8 is error-prone. Does it make more sense to do the +8 inside riscv_insn_c_sh_extract_xs2() and the likes? > + if (rd) { > + if (!fp) > + val.data_ulong = *(unsigned long *)((unsigned long *)regs + rd); > + else if (len == 8) > + val.data_u64 = get_f64_rs(rd, regs); > + else > + val.data_ulong = get_f32_rs(rd, regs); > + > + if (user_mode(regs)) { > + if (copy_to_user((u8 __user *)addr, &val, len)) > + return -1; > + } else { > + memcpy((u8 *)addr, &val, len); > + } > } Again, why the if (rd) condition? What if it is f0? Nam _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv