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Mon, 21 Feb 2022 10:06:33 +0000 Date: Mon, 21 Feb 2022 10:06:33 +0000 Message-ID: <87bkz04jpy.wl-maz@kernel.org> From: Marc Zyngier To: Anup Patel Cc: Anup Patel , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Daniel Lezcano , Atish Patra , Alistair Francis , linux-riscv , "linux-kernel@vger.kernel.org List" Subject: Re: [PATCH v3 2/6] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode In-Reply-To: References: <20220220050854.743420-1-apatel@ventanamicro.com> <20220220050854.743420-3-apatel@ventanamicro.com> <87czjg4kf4.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anup@brainfault.org, apatel@ventanamicro.com, palmer@dabbelt.com, paul.walmsley@sifive.com, tglx@linutronix.de, daniel.lezcano@linaro.org, atishp@atishpatra.org, Alistair.Francis@wdc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220221_020636_718948_C6E4219C X-CRM114-Status: GOOD ( 29.16 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, 21 Feb 2022 09:55:05 +0000, Anup Patel wrote: > > On Mon, Feb 21, 2022 at 3:21 PM Marc Zyngier wrote: > > > > On Sun, 20 Feb 2022 05:08:50 +0000, > > Anup Patel wrote: > > > > > > Various RISC-V drivers (such as SBI IPI, SBI Timer, SBI PMU, and > > > KVM RISC-V) don't have associated DT node but these drivers need > > > standard per-CPU (local) interrupts defined by the RISC-V privileged > > > specification. > > > > > > We add riscv_get_intc_hwnode() in arch/riscv which allows RISC-V > > > drivers not having DT node to discover INTC hwnode which in-turn > > > helps these drivers to map per-CPU (local) interrupts provided > > > by the INTC driver. > > > > > > Signed-off-by: Anup Patel > > > --- > > > arch/riscv/include/asm/irq.h | 4 ++++ > > > arch/riscv/kernel/irq.c | 19 +++++++++++++++++++ > > > drivers/irqchip/irq-riscv-intc.c | 7 +++++++ > > > 3 files changed, 30 insertions(+) > > > [...] > > > index b65bd8878d4f..fa24ecd01d39 100644 > > > --- a/drivers/irqchip/irq-riscv-intc.c > > > +++ b/drivers/irqchip/irq-riscv-intc.c > > > @@ -92,6 +92,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops = { > > > .xlate = irq_domain_xlate_onecell, > > > }; > > > > > > +static struct fwnode_handle *riscv_intc_hwnode(void) > > > +{ > > > + return (intc_domain) ? intc_domain->fwnode : NULL; > > > +} > > > > This makes no sense. Either you have found the interrupt controller > > and allocated the domain, or you haven't. But you don't register a > > callback without having found it. > > We are registering this callback after creating the INTC domain. Then why are you checking for intc_domain being NULL? > > And you have totally ignored my previous comments about the multitude > > of irq domains for the INTC. Either you get rid of all but one and you > > can register a single fwnode, or you stay with what you have today, > > Only the INTC DT nodes are per-CPU but we are creating only one > INTC domain to manage per-CPU IRQs across all CPUs. Ah, there is this guard that is only valid on the boot CPU. Fair enough. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv