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From: Thomas Gleixner <tglx@kernel.org>
To: Anup Patel <anup@brainfault.org>
Cc: LKML <linux-kernel@vger.kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-riscv@lists.infradead.org, Radu Rendec <radu@rendec.net>,
	Marc Zyngier <maz@kernel.org>, Paul Walmsley <pjw@kernel.org>
Subject: Re: Interrupt chip driver maintainence
Date: Sat, 05 Sep 2026 23:30:44 +0200	[thread overview]
Message-ID: <87ecf74c8r.ffs@fw13> (raw)
In-Reply-To: <CAAhSdy1=Z-VjEhGsGOJ15QptCSZP_6zG1NF=B972KwzEJhFbFg@mail.gmail.com>

On Sat, Sep 05 2026 at 16:37, Anup Patel wrote:
> On Fri, Sep 4, 2026 at 8:19 PM Thomas Gleixner <tglx@kernel.org> wrote:
>> I'm still going to pick up obvious and simple bug fixes, but for
>> anything which requires deep knowledge on the underlying hardware, I'm
>> going to just mark them obsolete when they molded in my inbox unreviewed
>> by the people who understand it for six weeks.
>>
>
> I think this is a fair ask.
>
> Currently, I am focused on reviewing and testing anything which
> touches RISC-V AIA drivers. The SiFive PLIC driver on other hand
> seems to have no active reivewers from RISC-V space. Few years
> back I did try to actively review SiFive PLIC driver but these days
> I don't have bandwidth for that.

I don't blame you and I put you on the CC list because you are in the
RISCV space.

I don't know what's wrong with SiFive but they really need to get their
act together. Paul?

Thanks,

        tglx

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      reply	other threads:[~2026-09-05 21:31 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-04 14:49 Interrupt chip driver maintainence Thomas Gleixner
2026-09-04 15:01 ` Marc Zyngier
2026-09-05  0:46 ` Radu Rendec
2026-09-05  2:51 ` Nam Cao
2026-09-05 19:12   ` Thomas Gleixner
2026-09-05 11:07 ` Anup Patel
2026-09-05 21:30   ` Thomas Gleixner [this message]

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