From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CFC9FC433FE for ; Wed, 30 Nov 2022 18:05:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+XZAPpgt3da36VcMlCbaL02i7b+M0Bg7gs5vUPIK848=; b=SR6CLxy3x8VIQU ghA3BX8P//rRHMjZCvyLmj5VImgfbkUOtu4cZUaLVfRA4dhJjWagTHmGKdjVpJZmsEDvf+t1BFmgQ PFRmVxnQoW2Hy8uRO3g5d8gTfIvkZnA0hLCfwNPBslUc05FGt3MM06m6O/PSR9WDX/0pivQ2BxSoJ 5Zil/s061umpfmZosmm5RKE0UOCIuU1hX2HwFb3jsdb6UUq/eaor19Zh9X+BGAaetxE9TFKlUxY05 7TZzUoyOg9UM4nC5vsvfodO/3LbgR3ZnjinNDekafPQDnUQS2EsbgVkpQFDmf4Oo2nYScMgtSGXMa cYkL9CzwL+MUHYyBY5gQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0RSg-001NVb-UM; Wed, 30 Nov 2022 18:05:34 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0RQC-001LGs-1A for linux-riscv@lists.infradead.org; Wed, 30 Nov 2022 18:03:02 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 94FBD61D23; Wed, 30 Nov 2022 18:02:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F0E1EC433D7; Wed, 30 Nov 2022 18:02:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1669831375; bh=Y9g7phTOGvNc4CFm3fAtwIfggfZ/yOOnreTfYzARfZ0=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=AKAaytmGy4nwo0o2XypCIP1SLXaibMtmFQYjTlLnYcPL3TlB01xbiZNsIplEOESVj f5DCVgc1txkD4EtOCo1kh5V+qF3vqN6am3iHZHNwiowyFEGK9nbhZxtabeMNk7VNXO 6T+xVbkTEBbjeMYy6Z4LVxQBCBhLwscACu2otNaYwtoezCHJ+Ye9O75dcKashEL/mj yJDTpdlI35BljepvO1zIGRqgg/Et4HGFbjDZI1DvO9Z9KjQwPNBo2EIANByBnrzJNJ WxPAvrUpWlBhx7wnEaWjsfPiqsj5JBDB0wr6sRPFVussoBRBltvUg43cd3k7w2tvNX If+pFYMl8jbKA== Received: from ip-185-104-136-29.ptr.icomera.net ([185.104.136.29] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1p0RQ2-009eMw-Ri; Wed, 30 Nov 2022 18:02:52 +0000 Date: Wed, 30 Nov 2022 18:02:29 +0000 Message-ID: <87o7sotj62.wl-maz@kernel.org> From: Marc Zyngier To: Anup Patel Cc: Anup Patel , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Daniel Lezcano , Atish Patra , Alistair Francis , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v13 4/7] RISC-V: Treat IPIs as normal Linux IRQs In-Reply-To: References: <20221129142449.886518-1-apatel@ventanamicro.com> <20221129142449.886518-5-apatel@ventanamicro.com> <86bkoomn4h.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.104.136.29 X-SA-Exim-Rcpt-To: anup@brainfault.org, apatel@ventanamicro.com, palmer@dabbelt.com, paul.walmsley@sifive.com, tglx@linutronix.de, daniel.lezcano@linaro.org, atishp@atishpatra.org, Alistair.Francis@wdc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221130_100300_202713_D374CCB8 X-CRM114-Status: GOOD ( 38.47 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, 30 Nov 2022 17:14:09 +0000, Anup Patel wrote: > > On Wed, Nov 30, 2022 at 9:48 PM Marc Zyngier wrote: > > > > On Tue, 29 Nov 2022 14:24:46 +0000, > > Anup Patel wrote: > > > > > > Currently, the RISC-V kernel provides arch specific hooks (i.e. > > > struct riscv_ipi_ops) to register IPI handling methods. The stats > > > gathering of IPIs is also arch specific in the RISC-V kernel. > > > > > > Other architectures (such as ARM, ARM64, and MIPS) have moved away > > > from custom arch specific IPI handling methods. Currently, these > > > architectures have Linux irqchip drivers providing a range of Linux > > > IRQ numbers to be used as IPIs and IPI triggering is done using > > > generic IPI APIs. This approach allows architectures to treat IPIs > > > as normal Linux IRQs and IPI stats gathering is done by the generic > > > Linux IRQ subsystem. > > > > > > We extend the RISC-V IPI handling as-per above approach so that arch > > > specific IPI handling methods (struct riscv_ipi_ops) can be removed > > > and the IPI handling is done through the Linux IRQ subsystem. > > > > > > Signed-off-by: Anup Patel > > > --- > > > arch/riscv/Kconfig | 2 + > > > arch/riscv/include/asm/sbi.h | 10 +- > > > arch/riscv/include/asm/smp.h | 35 ++++--- > > > arch/riscv/kernel/Makefile | 1 + > > > arch/riscv/kernel/cpu-hotplug.c | 3 +- > > > arch/riscv/kernel/irq.c | 3 +- > > > arch/riscv/kernel/sbi-ipi.c | 81 ++++++++++++++++ > > > arch/riscv/kernel/sbi.c | 106 +++----------------- > > > arch/riscv/kernel/smp.c | 155 +++++++++++++++--------------- > > > arch/riscv/kernel/smpboot.c | 5 +- > > > drivers/clocksource/timer-clint.c | 65 ++++++++++--- > > > drivers/irqchip/Kconfig | 1 + > > > drivers/irqchip/irq-riscv-intc.c | 55 +++++------ > > > 13 files changed, 287 insertions(+), 235 deletions(-) > > > create mode 100644 arch/riscv/kernel/sbi-ipi.c > > > > > > > [...] > > > > > diff --git a/arch/riscv/kernel/sbi-ipi.c b/arch/riscv/kernel/sbi-ipi.c > > > new file mode 100644 > > > index 000000000000..6466706b03a7 > > > --- /dev/null > > > +++ b/arch/riscv/kernel/sbi-ipi.c > > > @@ -0,0 +1,81 @@ > > > +// SPDX-License-Identifier: GPL-2.0-only > > > +/* > > > + * Multiplex several IPIs over a single HW IPI. > > > + * > > > + * Copyright (c) 2022 Ventana Micro Systems Inc. > > > + */ > > > + > > > +#define pr_fmt(fmt) "riscv: " fmt > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +static int sbi_ipi_virq; > > > +static DEFINE_PER_CPU_READ_MOSTLY(int, sbi_ipi_dummy_dev); > > > + > > > +static irqreturn_t sbi_ipi_handle(int irq, void *dev_id) > > > +{ > > > + csr_clear(CSR_IP, IE_SIE); > > > + ipi_mux_process(); > > > + return IRQ_HANDLED; > > > > Urgh... I really wish I hadn't seen this. This requires a chained > > handler. You had it before, and yet you dropped it. Why? > > > > Either you call ipi_mux_process() from your root interrupt controller, > > or you implement a chained handler. But not this. > > > > Same thing about the clint stuff. > > We had chained handler all along but there is problem (which > was pointed to us) in using chained handler because the parent > RISC-V INTC irqchip driver does not have irq_eoi() so the > chained_irq_enter() and chained_irq_exit() will do the interrupt > mask/unmask dance which seems unnecessary. > > Is there a better way to avoid the interrupt mask/unmask dance ? Well, you could have an IPI-specific irqchip, with an empty EOI callback. Or something. But not *that*. And next time you change something of that importance, add it to your change log. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv