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Sat, 16 Jul 2022 18:52:06 +0100 Date: Sat, 16 Jul 2022 18:52:01 +0100 Message-ID: <87o7xp3pz2.wl-maz@kernel.org> From: Marc Zyngier To: Cc: , , , , , , , Subject: Re: [PATCH v3 1/1] gpio: mpfs: add polarfire soc gpio support In-Reply-To: <2d7f72d3e89686d3ba5cff5df8cfe443d04fc5f4.camel@microchip.com> References: <20220716071113.1646887-1-lewis.hanly@microchip.com> <20220716071113.1646887-2-lewis.hanly@microchip.com> <87r12l4aaj.wl-maz@kernel.org> <2d7f72d3e89686d3ba5cff5df8cfe443d04fc5f4.camel@microchip.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.104.136.29 X-SA-Exim-Rcpt-To: Lewis.Hanly@microchip.com, linux-riscv@lists.infradead.org, Conor.Dooley@microchip.com, brgl@bgdev.pl, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, palmer@dabbelt.com, linux-kernel@vger.kernel.org, Daire.McNamara@microchip.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220716_105218_049724_96CD77F4 X-CRM114-Status: GOOD ( 20.92 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sat, 16 Jul 2022 16:21:48 +0100, wrote: > > Thanks Marc, > > On Sat, 2022-07-16 at 11:33 +0100, Marc Zyngier wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you > > know the content is safe > > > > On Sat, 16 Jul 2022 08:11:13 +0100, > > wrote: > > > From: Lewis Hanly > > > > > > Add a driver to support the Polarfire SoC gpio controller. > > > > > > Signed-off-by: Lewis Hanly > > > > [...] > > > > > +static int mpfs_gpio_child_to_parent_hwirq(struct gpio_chip *gc, > > > + unsigned int child, > > > + unsigned int child_type, > > > + unsigned int *parent, > > > + unsigned int *parent_type) > > > +{ > > > + struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc); > > > + struct irq_data *d = irq_get_irq_data(mpfs_gpio- > > > >irq_number[child]); > > > > This looks totally wrong. It means that you have already instantiated > > part of the hierarchy, and it is likely that you will get multiple > > hierarchy sharing some levels, which isn't intended. > > Some background why I use the above. > We need to support both direct and non-direct IRQ connections to the > PLIC. > In direct mode the GPIO IRQ's are connected directly to the PLIC and > certainly no need for the above. GPIO's can also be configured in non- > direct, which means they use a shared IRQ, hence the above. That's unfortunately not acceptable. You need to distinguish which one is which, and separate them. Your non-direct mode certainly requires special handling, and is not fit for a hierarchical mode. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv