From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AAD32C433EF for ; Sat, 16 Jul 2022 10:33:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Z0wcrGKM6a56ajhxP+T2J5vRfKK9Z2RbmVbFNGzYBRs=; b=2Fbb3bymX88cOi z8cDzL1/G9Jy3RSr+zDY2m1rassgCnICqUIcrHcrw9jNieh8ZY0I1ZjDO9CDE3to/nDNa0VAuS37L unJNy5Xo86N+fQwXX3vDWOVJi9u5+H8YX4vp5pByEyr0xqPQ0EfwtGTl2YbbPrGEguUe/e0MjR0Jf piABRIJZw0I5POrEBmRLAfTx22xlxVsoIKYijMvTUuLs1vfGPQipNMllgPLHm9DgNOYHS79dQhz3u GETyQFKRGOD7xKmAcmCZVfTUkav8wuH9f+VK5xcEO2hkhv5qn9b3VA2dsLoGpjXYTuSX7c5Dqv+TC 2E+BTWXffJNK5nuZFYEg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oCf70-00FOs8-9k; Sat, 16 Jul 2022 10:33:26 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oCf6x-00FOor-Br for linux-riscv@lists.infradead.org; Sat, 16 Jul 2022 10:33:25 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 452D7B82EEA; Sat, 16 Jul 2022 10:33:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E8ACAC34114; Sat, 16 Jul 2022 10:33:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657967598; bh=fb7zcFr0KnXxkQp0xpdk4Mcd+9GKD+xwhdHZmcfcxGM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=SFmHR5nFB+nKOqpu5Q04w6uop28XC7xK6cMvxDQaREF2HMd6r3jtvPck5KRlWzpPt ZAqPYOh3GcX7t1x08di4o+ogeZcjpS5gbe7lLzRcDOXhNLhpqHuJmttXcT79B9TNU6 zip+sWCL1VN2i1A37PvY70STaJWY8ViWKU+cdVEfepMom4cXEGNe/yvbpIxu5k16f+ GkDkLw6B8ooc17oyg4WHKA5Gu9oQ0sphFtAEbIRRPX1jD+G7BQwzQZufSlvVfmeA4n kGnzZ/L1Ln64G+T76u3rYxNu4QxL45rP36+edMzzWb+U+zyVoS4mCoOU1TFN3OJfnM eQSH9r4o8AWSQ== Received: from ip-185-104-136-29.ptr.icomera.net ([185.104.136.29] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oCf6p-007rDL-Ga; Sat, 16 Jul 2022 11:33:15 +0100 Date: Sat, 16 Jul 2022 11:33:08 +0100 Message-ID: <87r12l4aaj.wl-maz@kernel.org> From: Marc Zyngier To: Cc: , , , , , , , Subject: Re: [PATCH v3 1/1] gpio: mpfs: add polarfire soc gpio support In-Reply-To: <20220716071113.1646887-2-lewis.hanly@microchip.com> References: <20220716071113.1646887-1-lewis.hanly@microchip.com> <20220716071113.1646887-2-lewis.hanly@microchip.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.104.136.29 X-SA-Exim-Rcpt-To: lewis.hanly@microchip.com, linux-gpio@vger.kernel.org, linux-riscv@lists.infradead.org, linus.walleij@linaro.org, brgl@bgdev.pl, linux-kernel@vger.kernel.org, palmer@dabbelt.com, conor.dooley@microchip.com, daire.mcnamara@microchip.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220716_033323_723408_91A43D87 X-CRM114-Status: GOOD ( 22.09 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sat, 16 Jul 2022 08:11:13 +0100, wrote: > > From: Lewis Hanly > > Add a driver to support the Polarfire SoC gpio controller. > > Signed-off-by: Lewis Hanly [...] > +static int mpfs_gpio_child_to_parent_hwirq(struct gpio_chip *gc, > + unsigned int child, > + unsigned int child_type, > + unsigned int *parent, > + unsigned int *parent_type) > +{ > + struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc); > + struct irq_data *d = irq_get_irq_data(mpfs_gpio->irq_number[child]); This looks totally wrong. It means that you have already instantiated part of the hierarchy, and it is likely that you will get multiple hierarchy sharing some levels, which isn't intended. > + *parent_type = IRQ_TYPE_NONE; > + *parent = irqd_to_hwirq(d); > + > + return 0; > +} > + > +static int mpfs_gpio_probe(struct platform_device *pdev) > +{ > + struct clk *clk; > + struct device *dev = &pdev->dev; > + struct device_node *node = pdev->dev.of_node; > + struct device_node *irq_parent; > + struct gpio_irq_chip *girq; > + struct irq_domain *parent; > + struct mpfs_gpio_chip *mpfs_gpio; > + int i, ret, ngpio; > + > + mpfs_gpio = devm_kzalloc(dev, sizeof(*mpfs_gpio), GFP_KERNEL); > + if (!mpfs_gpio) > + return -ENOMEM; > + > + mpfs_gpio->base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(mpfs_gpio->base)) > + return dev_err_probe(dev, PTR_ERR(mpfs_gpio->clk), "input clock not found.\n"); > + > + clk = devm_clk_get(dev, NULL); > + if (IS_ERR(clk)) > + return dev_err_probe(dev, PTR_ERR(clk), "devm_clk_get failed\n"); > + > + ret = clk_prepare_enable(clk); > + if (ret) > + return dev_err_probe(dev, ret, "failed to enable clock\n"); > + > + mpfs_gpio->clk = clk; > + > + ngpio = of_irq_count(node); > + if (ngpio > NUM_GPIO) { > + ret = -ENXIO; > + goto cleanup_clock; > + } > + > + irq_parent = of_irq_find_parent(node); > + if (!irq_parent) { > + ret = -ENODEV; > + goto cleanup_clock; > + } > + parent = irq_find_host(irq_parent); > + if (!parent) { > + ret = -ENODEV; > + goto cleanup_clock; > + } > + > + /* Get the interrupt numbers. */ > + /* Clear/Disable All interrupts before enabling parent interrupts. */ > + for (i = 0; i < ngpio; i++) { > + mpfs_gpio->irq_number[i] = platform_get_irq(pdev, i); Bingo. You are allocating the interrupt for the level below. You really shouldn't do that. If you need to retrieve the *hwirq* for the level below, you need to parse the DT without triggering an IRQ allocation (of_irq_parse_one() and co). M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv