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a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1760553648; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=+uP+eUWmeV1AcOzpTFqHijqsFbONeijvS4FICr7ALx0=; b=UYfg96jVV87s4/TO5Vuc6hNOWjzMJp5IqRYwlMW4j71Ncv1gUmSo08Rx6c6uwktqSx9/6i D/+JC7X2WVknTiCg== To: Lucas Zampieri , linux-kernel@vger.kernel.org Cc: Charles Mirabile , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Vivian Wang , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Zhang Xincheng , Lucas Zampieri Subject: Re: [PATCH v4 3/3] irqchip/plic: add support for UltraRISC DP1000 PLIC In-Reply-To: <20251015143108.441291-4-lzampier@redhat.com> References: <20251015143108.441291-1-lzampier@redhat.com> <20251015143108.441291-4-lzampier@redhat.com> Date: Wed, 15 Oct 2025 20:40:47 +0200 Message-ID: <87y0pc100g.ffs@tglx> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251015_114052_052509_3E2594F6 X-CRM114-Status: GOOD ( 19.52 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Oct 15 2025 at 15:31, Lucas Zampieri wrote: > +static bool cp100_isolate_pending_irq(int nr_irq_groups, u32 ie[], > + void __iomem *pending, > + void __iomem *enable) > +{ > + u32 pending_irqs = 0; > + int i, j; > + > + /* Look for first pending interrupt */ > + for (i = 0; i < nr_irq_groups; i++) { > + pending_irqs = ie[i] & readl_relaxed(pending + i * sizeof(u32)); > + if (pending_irqs) > + break; > + } > + > + if (!pending_irqs) > + return false; > + > + /* Disable all interrupts but the first pending one */ > + for (j = 0; j < nr_irq_groups; j++) { > + u32 new_mask = 0; > + > + if (j == i) > + /* Extract mask with lowest set bit */ > + new_mask = (pending_irqs & -pending_irqs); Please add brackets around the conditional as it's not a true single line. > +static irq_hw_number_t cp100_get_hwirq(struct plic_handler *handler, > + void __iomem *claim) > +{ > + void __iomem *enable = handler->enable_base; > + void __iomem *pending = handler->priv->regs + PENDING_BASE; > + int nr_irqs = handler->priv->nr_irqs; > + int nr_irq_groups = DIV_ROUND_UP(nr_irqs, 32); > + int i; > + irq_hw_number_t hwirq = 0; Please use reverse fir tree ordering: https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#variable-declarations > + > + raw_spin_lock(&handler->enable_lock); Please use guard(raw_spinlock)(&handler->....); which gets rid of the goto and you can just return instead. > + /* Save current interrupt enable state */ > + for (i = 0; i < nr_irq_groups; i++) > + handler->enable_save[i] = readl_relaxed(enable + i * sizeof(u32)); > + > + if (!cp100_isolate_pending_irq(nr_irq_groups, handler->enable_save, pending, enable)) > + goto out; > + > + hwirq = readl(claim); > + > + /* Restore previous state */ > + for (i = 0; i < nr_irq_groups; i++) > + writel_relaxed(handler->enable_save[i], enable + i * sizeof(u32)); > +out: > + raw_spin_unlock(&handler->enable_lock); > + return hwirq; > +} > + > +static void plic_handle_irq_cp100(struct irq_desc *desc) > +{ > + struct plic_handler *handler = this_cpu_ptr(&plic_handlers); > + struct irq_chip *chip = irq_desc_get_chip(desc); > + void __iomem *claim = handler->hart_base + CONTEXT_CLAIM; > + irq_hw_number_t hwirq; > + > + WARN_ON_ONCE(!handler->present); > + > + chained_irq_enter(chip, desc); > + > + while ((hwirq = cp100_get_hwirq(handler, claim))) { > + int err = generic_handle_domain_irq(handler->priv->irqdomain, > + hwirq); Let it stick out, you have 100 characters > + if (unlikely(err)) { > + pr_warn_ratelimited("%pfwP: can't find mapping for hwirq %lu\n", > + handler->priv->fwnode, hwirq); > + } > + } > + > + chained_irq_exit(chip, desc); > +} > + > static void plic_set_threshold(struct plic_handler *handler, u32 threshold) > { > /* priority must be > threshold to trigger an interrupt */ > @@ -430,6 +516,8 @@ static const struct of_device_id plic_match[] = { > .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) }, > { .compatible = "thead,c900-plic", > .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) }, > + { .compatible = "ultrarisc,cp100-plic", > + .data = (const void *)BIT(PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM) }, > {} > }; > > @@ -664,12 +752,16 @@ static int plic_probe(struct fwnode_handle *fwnode) > } > > if (global_setup) { > + void (*handler_fn)(struct irq_desc *) = plic_handle_irq; Lacks a newline between variable declaration and code. > + if (test_bit(PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM, &handler->priv->plic_quirks)) > + handler_fn = plic_handle_irq_cp100; > + > /* Find parent domain and register chained handler */ > domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_ANY); > if (domain) > plic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT); > if (plic_parent_irq) > - irq_set_chained_handler(plic_parent_irq, plic_handle_irq); > + irq_set_chained_handler(plic_parent_irq, handler_fn); > > cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, > "irqchip/sifive/plic:starting", Thanks, tglx _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv