Re: [PATCH 00/17] Prctl to enable vector commands, previous vector patches rebased

Conor Dooley
2022-09-21T17:14:43Z

On Wed, Sep 21, 2022 at 09:44:43AM -0700, Chris Stillson wrote:
> This patch adds a prctl to enable, disable, or query whether vectors
> are enabled or not.
> This is to allow a process to "opt out" of the overhead incurred by
> using vectors. Because this
> is build on top of an existing set of patches to work with vectors,
> they have been rebased to
> Linux 6.0-rc1.

Hey Chris,
Any other review aside - it looks like this patchset has been oddly
sent. Did you by any chance copy paste the patches into gmail?

May you should speak with Atish or Palmer about how to set up your
environment to use git send-email. "Our" tools expect that a series of
patches is threaded so that tools like `b4` can pull the lot down
from lore.kernel.org etc. git send-email will do that for you for free.

Secondly, it looks like in many of the patches you are not the author,
so you there's a "From: blah blan <blah@blah.com>" missing from them
which happens when you copy a patch but again send-email will sort out
for you.

The signed-off-by chains on a lot of mails look wrong too, mostly they
are missing your SoB since you are the sender.

Finally, please run get_maintainer.pl - there are KVM patches in here
and you have not CCed the KVM maintainers (nor have you CCed the people
who wrote the patches in the first place).

Reading the "submitting patches" document might be helpful to you:
https://docs.kernel.org/process/submitting-patches.html

Thanks,
Conor.

>
>
> Chris Stillson (1):
> riscv: prctl to enable vector commands
>
> Greentime Hu (9):
> riscv: Add new csr defines related to vector extension
> riscv: Add has_vector/riscv_vsize to save vector features.
> riscv: Add vector struct and assembler definitions
> riscv: Add task switch support for vector
> riscv: Add ptrace vector support
> riscv: Add sigcontext save/restore for vector
> riscv: Add support for kernel mode vector
> riscv: Add vector extension XOR implementation
> riscv: Fix a kernel panic issue if $s2 is set to a specific value
> before entering Linux
>
> Guo Ren (4):
> riscv: Rename __switch_to_aux -> fpu
> riscv: Extending cpufeature.c to detect V-extension
> riscv: Add vector feature to compile
> riscv: Reset vector register
>
> Vincent Chen (3):
> riscv: signal: Report signal frame size to userspace via auxv
> riscv: Add V extension to KVM ISA allow list
> riscv: KVM: Add vector lazy save/restore support
>
> arch/riscv/Kconfig | 15 +-
> arch/riscv/Makefile | 1 +
> arch/riscv/configs/defconfig | 6 +
> arch/riscv/include/asm/csr.h | 16 ++-
> arch/riscv/include/asm/elf.h | 47 +++---
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/include/asm/kvm_host.h | 2 +
> arch/riscv/include/asm/kvm_vcpu_vector.h | 65 +++++++++
> arch/riscv/include/asm/processor.h | 9 ++
> arch/riscv/include/asm/switch_to.h | 83 ++++++++++-
> arch/riscv/include/asm/vector.h | 17 +++
> arch/riscv/include/asm/xor.h | 82 +++++++++++
> arch/riscv/include/uapi/asm/auxvec.h | 1 +
> arch/riscv/include/uapi/asm/hwcap.h | 1 +
> arch/riscv/include/uapi/asm/kvm.h | 7 +
> arch/riscv/include/uapi/asm/ptrace.h | 23 +++
> arch/riscv/include/uapi/asm/sigcontext.h | 24 ++++
> arch/riscv/kernel/Makefile | 2 +
> arch/riscv/kernel/asm-offsets.c | 15 ++
> arch/riscv/kernel/cpufeature.c | 21 +++
> arch/riscv/kernel/entry.S | 6 +-
> arch/riscv/kernel/head.S | 37 ++++-
> arch/riscv/kernel/kernel_mode_vector.c | 132 +++++++++++++++++
> arch/riscv/kernel/process.c | 61 ++++++++
> arch/riscv/kernel/ptrace.c | 71 ++++++++++
> arch/riscv/kernel/riscv_ksyms.c | 6 +
> arch/riscv/kernel/signal.c | 173 ++++++++++++++++++++++-
> arch/riscv/kernel/vector.S | 102 +++++++++++++
> arch/riscv/kvm/Makefile | 1 +
> arch/riscv/kvm/vcpu.c | 32 +++++
> arch/riscv/kvm/vcpu_switch.S | 69 +++++++++
> arch/riscv/kvm/vcpu_vector.c | 173 +++++++++++++++++++++++
> arch/riscv/lib/Makefile | 1 +
> arch/riscv/lib/xor.S | 81 +++++++++++
> include/uapi/linux/elf.h | 1 +
> include/uapi/linux/prctl.h | 6 +
> kernel/sys.c | 7 +
> 37 files changed, 1355 insertions(+), 42 deletions(-)
> create mode 100644 arch/riscv/include/asm/kvm_vcpu_vector.h
> create mode 100644 arch/riscv/include/asm/vector.h
> create mode 100644 arch/riscv/include/asm/xor.h
> create mode 100644 arch/riscv/kernel/kernel_mode_vector.c
> create mode 100644 arch/riscv/kernel/vector.S
> create mode 100644 arch/riscv/kvm/vcpu_vector.c
> create mode 100644 arch/riscv/lib/xor.S
>
> --
> 2.25.1
>
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