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([2a01:e34:ed2f:f020:e504:4297:986:ffb0]) by smtp.googlemail.com with ESMTPSA id q17sm4243965wmk.36.2020.05.19.06.51.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 May 2020 06:51:09 -0700 (PDT) Subject: Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val To: Kefeng Wang , Palmer Dabbelt , tglx@linutronix.de References: <66121f9a-48f3-d3a5-7c96-d71397e12aed@linaro.org> <0bc3eb36-7b9d-7c86-130c-68b566e85c10@huawei.com> <29dc112e-d8c2-2749-7f5d-7c0c19aa9092@huawei.com> From: Daniel Lezcano Message-ID: <8c5ecbd3-c23a-ccd4-b5d8-2e7d2bd10699@linaro.org> Date: Tue, 19 May 2020 15:51:08 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <29dc112e-d8c2-2749-7f5d-7c0c19aa9092@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200519_065113_608675_91AD8130 X-CRM114-Status: GOOD ( 15.16 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hulkci@huawei.com, linux-riscv@lists.infradead.org, aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org, Paul Walmsley Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On 19/05/2020 14:39, Kefeng Wang wrote: > > On 2020/5/19 4:23, Daniel Lezcano wrote: >> Hi Kefeng, >> >> On 18/05/2020 17:40, Kefeng Wang wrote: >>> On 2020/5/18 22:09, Daniel Lezcano wrote: >>>> On 13/05/2020 23:14, Palmer Dabbelt wrote: >>>>> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com >>>>> wrote: >>>>>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined! >>>>>> >>>>>> Reported-by: Hulk Robot >>>>>> Signed-off-by: Kefeng Wang >>>>>> --- >>>>>>    drivers/clocksource/timer-riscv.c | 1 + >>>>>>    1 file changed, 1 insertion(+) >>>>>> >>>>>> diff --git a/drivers/clocksource/timer-riscv.c >>>>>> b/drivers/clocksource/timer-riscv.c >>>>>> index c4f15c4068c0..071b8c144027 100644 >>>>>> --- a/drivers/clocksource/timer-riscv.c >>>>>> +++ b/drivers/clocksource/timer-riscv.c >>>>>> @@ -19,6 +19,7 @@ >>>>>> >>>>>>    u64 __iomem *riscv_time_cmp; >>>>>>    u64 __iomem *riscv_time_val; >>>>>> +EXPORT_SYMBOL(riscv_time_val); >>>>>> >>>>>>    static inline void mmio_set_timer(u64 val) >>>>>>    { >>>>> Reviewed-by: Palmer Dabbelt >>>>> Acked-by: Palmer Dabbelt >>>>> >>>>> Adding the clocksource maintainers.  Let me know if you want this >>>>> through my >>>>> tree, I'm assuming you want it through your tree. >>>> How can we end up by an export symbol here ?! >>> Hi Danile, >> s/Danile/Daniel/ > Sorry for typing error. >> >>> Found this build error when CONFIG_RISCV_M_MODE=y and CONFIG_RISCV_SBI >>> is not, >>> >>> see patch "4f9bbcefa142 riscv: add support for MMIO access to the timer >>> registers" >> Thanks for the pointer. >> >> The question still remains, how do we end up with this EXPORT_SYMBOL? >> >> There is something wrong if the fix is an EXPORT_SYMBOL for a global >> variable. > > Not very clear, there are some global variable( eg, acpi_disabled, > memstart_addr in arm64,) is exported by EXPORT_SYMBOL,  do you mean that > export riscv_time_val is wrong way? I do not maintain acpi neither arm64.mm. AFAICT, riscv_time_val is globally declared in drivers/clocksource/timer-riscv.c The driver does not use this variable at all. Then there is a readl on it in the header file arch/riscv/include/asm/timex.h And finally it is initialized in arch/riscv/kernel/clint.c Same thing for riscv_time_cmp. The correct fix is to initialize the variables in the place where they belong to (drivers/clocksource/timer-riscv.c), create a function to read their content and export-symbol-gpl the function. -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog