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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrgq8-0000000C0TG-3h8T; Tue, 02 Apr 2024 16:18:24 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrgq4-0000000C0Rv-3pw8 for linux-riscv@lists.infradead.org; Tue, 02 Apr 2024 16:18:22 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 139ABCE10EF; Tue, 2 Apr 2024 16:18:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CD868C433C7; Tue, 2 Apr 2024 16:18:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712074696; bh=tqIuMZfC4MsoHlk9HVhKG/9PpH5oRCBJruwdKEA1VZw=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=DJDRrDbNLGOiNgFd3/HXrhBy/yplIQOUciqf0NwEUhNc72OkVudEPXLgseBuiTuH4 pUA3CN2l7ysl7ggJ34ZEsWQ7OFWB5VHUASq0qWrCkNd/XjeUaXzeyROLPwyqYDErUE lOBbvSaXwblHk4UiHlCfUmsQFGef9Z/F4EqEYjVhWWnGtfj7ZPnhhvW4I59deE5x2r cHMZmr3qnkY9FnT16mx1+RdGMgM2zEHDH6ldN2F0WOuCUXUNdLjltPRgEPPmg+6EwU gDwCDAzmLWBsmutde7WRplqOrZ5LgeqtJUg7wsi5USu3F/XEFULPbLJQqtjrTtZ5Lh xQPC+Do4UQCfQ== Message-ID: <8d21b1bc-9402-41d4-bd81-c521c8a33d2d@kernel.org> Date: Tue, 2 Apr 2024 18:18:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] clk: starfive: pll: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz To: Xingyu Wu , Michael Turquette , Stephen Boyd , Conor Dooley , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org References: <20240402090920.11627-1-xingyu.wu@starfivetech.com> Content-Language: en-US From: Krzysztof Kozlowski Autocrypt: addr=krzk@kernel.org; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 02/04/2024 11:09, Xingyu Wu wrote: > CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. > But now PLL0 rate is 1GHz and the cpu frequency loads become > 333/500/500/1000MHz in fact. > > So PLL0 rate should be default set to 1.5GHz. But setting the > PLL0 rate need certain steps: > > 1. Change the parent of cpu_root clock to OSC clock. > 2. Change the divider of cpu_core if PLL0 rate is higher than > 1.25GHz before CPUfreq boot. > 3. Change the parent of cpu_root clock back to PLL0 clock. > > Reviewed-by: Hal Feng > Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") > Signed-off-by: Xingyu Wu > --- > > Hi Stephen and Emil, > > This patch fixes the issue about lower rate of CPUfreq[1] by setting PLL0 > rate to 1.5GHz. > > In order not to affect the cpu operation, setting the PLL0 rate need > certain steps. The cpu_root's parent clock should be changed first. And > the divider of the cpu_core clock should be set to 2 so they won't crash > when setting 1.5GHz without voltage regulation. Due to PLL driver boot > earlier than SYSCRG driver, cpu_core and cpu_root clocks are using by > ioremap(). > > [1]: https://github.com/starfive-tech/VisionFive2/issues/55 > > Previous patch link: > v2: https://lore.kernel.org/all/20230821152915.208366-1-xingyu.wu@starfivetech.com/ > v1: https://lore.kernel.org/all/20230811033631.160912-1-xingyu.wu@starfivetech.com/ > > Thanks, > Xingyu Wu > --- > .../jh7110-starfive-visionfive-2.dtsi | 5 + > .../clk/starfive/clk-starfive-jh7110-pll.c | 102 ++++++++++++++++++ Please do not mix DTS and driver code. That's not really portable. DTS is being exported and used in other projects. ... > > @@ -458,6 +535,8 @@ static int jh7110_pll_probe(struct platform_device *pdev) > struct jh7110_pll_priv *priv; > unsigned int idx; > int ret; > + struct device_node *np; > + struct resource res; > > priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); > if (!priv) > @@ -489,6 +568,29 @@ static int jh7110_pll_probe(struct platform_device *pdev) > return ret; > } > > + priv->is_first_set = true; > + np = of_find_compatible_node(NULL, NULL, "starfive,jh7110-syscrg"); Your drivers should not do it. It's fragile, hides true link/dependency. Please use phandles. > + if (!np) { > + ret = PTR_ERR(np); > + dev_err(priv->dev, "failed to get syscrg node\n"); > + goto np_put; > + } > + > + ret = of_address_to_resource(np, 0, &res); > + if (ret) { > + dev_err(priv->dev, "failed to get syscrg resource\n"); > + goto np_put; > + } > + > + priv->syscrg_base = ioremap(res.start, resource_size(&res)); > + if (!priv->syscrg_base) > + ret = -ENOMEM; Why are you mapping other device's IO? How are you going to ensure synced access to registers? Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv