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Fri, 18 Sep 2026 09:18:43 -0700 (PDT) Received: from [192.168.50.100] ([111.199.57.13]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39e55895112sm1814952a91.3.2026.09.18.09.18.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Sep 2026 09:18:43 -0700 (PDT) Message-ID: <90826872-1374-49e4-832d-555abf8e8369@gmail.com> Date: Sat, 19 Sep 2026 00:18:34 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v4 08/10] iommu/riscv: Pre-enable GADE for second-stage domains To: fangyu.yu@linux.alibaba.com Cc: guoren@kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com, jroedel@suse.de, zong.li@sifive.com, andrew.jones@oss.qualcomm.com, anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca, kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com, vasant.hegde@amd.com, joerg.roedel@amd.com, gong.shuai@sanechips.com.cn References: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> <20260915032828.11250-9-fangyu.yu@linux.alibaba.com> From: Gong Shuai In-Reply-To: <20260915032828.11250-9-fangyu.yu@linux.alibaba.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260918_091845_300560_7DBF0349 X-CRM114-Status: GOOD ( 17.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Fangyu, On 9/15/2026 11:28 AM, fangyu.yu@linux.alibaba.com wrote: > From: Fangyu Yu > > Pre-enable RISCV_IOMMU_DC_TC_GADE in the device context when > attaching a second-stage domain, if the IOMMU supports AMO_HWAD. > > Software pre-populates second-stage page tables with D set, so > enabling GADE by default does not change normal behavior. When > dirty tracking is enabled, iommufd clears the pre-set D bits and > GADE becomes necessary for hardware to update the dirty bit on > write access. > > This avoids toggling GADE dynamically and keeps device context > setup consistent with second-stage domain attachment. > > Signed-off-by: Fangyu Yu > --- > drivers/iommu/riscv/iommu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c > index 16779877351b..f01fd4e2f840 100644 > --- a/drivers/iommu/riscv/iommu.c > +++ b/drivers/iommu/riscv/iommu.c > @@ -1330,6 +1330,8 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, > FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_mode) | > FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) | > FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn); > + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD) > + dc.tc |= RISCV_IOMMU_DC_TC_GADE; I might be missing something, but I don't see how the GADE bit set here reaches the hardware IOMMU DC. In riscv_iommu_iodir_update() (in patch 04/10), it looks like only the V bit is taken: tc = READ_ONCE(dc->tc); tc |= new_dc->ta & RISCV_IOMMU_DC_TC_V; ... WRITE_ONCE(dc->tc, tc); I saw that you mentioned you tested it on QEMU. As far as I know, mainline QEMU has not yet declared the AMO_HWAD capability. Could you clarify whether you used a modified QEMU for this test? Thanks, Shuai > } else { > if (!riscv_iommu_fsc_supported(iommu, pt_info.fsc_iosatp_mode)) > return -ENODEV; _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv