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From: "Heiko Stübner" <heiko@sntech.de>
To: Palmer Dabbelt <palmer@dabbelt.com>, Stefan O'Rear <sorear@fastmail.com>
Cc: linux-riscv@lists.infradead.org, samuel@sholland.org,
	guoren@kernel.org, christoph.muellner@vrull.eu,
	conor.dooley@microchip.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC 2/2] RISC-V: add T-Head vector errata handling
Date: Thu, 22 Jun 2023 22:35:50 +0200	[thread overview]
Message-ID: <9132027.CDJkKcVGEf@diego> (raw)
In-Reply-To: <23381fc8-c297-46ed-9e11-a2643e18e4c9@app.fastmail.com>

Hi Stefan,

Am Donnerstag, 22. Juni 2023, 20:58:37 CEST schrieb Stefan O'Rear:
> On Thu, Jun 22, 2023, at 1:39 PM, Heiko Stübner wrote:
> > Am Dienstag, 13. Juni 2023, 08:35:53 CEST schrieb Stefan O'Rear:
> >> vxrm and vxsat are part of fcsr in 0.7.1, so they should already have been
> >> handled by __fstate_save and __fstate_restore, and this code is likely to
> >> misbehave (saving the new process's vxrm/vxsat in the old process's save area
> >> because float state is swapped before vector state in __switch_to).
> >
> > I'm not sure I follow your description but may be overlooking or have
> > misunderstood something.
> >
> > Somehow I way to often have trouble resolving CSR addresses, but according
> > to openSBI, FCSR has the location of 0x3
> > (#define CSR_FCSR 0x003 in include/sbi/riscv_encoding.h)
> >
> > where CSR_VXSAT and CSR_VXRM are at 0x9 and 0xa respectively.
> > (#define CSR_VXSAT 0x9 and  #define CSR_VXRM 0xa)
> >
> >
> > And looking at __fstate_save + __fstate_restore the only CSRs accessed seem
> > to be CSR_STATUS and FCSR itself.
> >
> > I definitly won't claim to be right, but don't see the issue yet.
> >
> >
> > Thanks for a hint
> > Heiko
> 
> Are you aware of "3.7. Vector Fixed-Point Fields in fcsr" in
> riscv-v-spec-0.7.1.pdf?

oh wow, thanks a lot for that pointer, now I understand your concern.

So in vector-0.7.1 fcsr[10:9] mirrors vxrm and fcsr[8] mirrors vxsat.


On a positive note, the T-Head cores seem to not implement the full
vector 0.7.1 specification after all, in the documentation I have [0]
fcsr[31:8] are declared as "0" and uppermost bits are [7:5] for the "frm"
field.

So I guess a code comment should suffice to explain :-)


Regards
Heiko


[0] https://github.com/T-head-Semi/openc906/blob/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
16.3.1.3 浮点控制状态寄存器（FCSR） on page 334



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  reply	other threads:[~2023-06-22 20:36 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-28 21:54 [PATCH RFC 0/2] RISC-V: T-Head vector handling Heiko Stuebner
2023-02-28 21:54 ` [PATCH RFC 1/2] RISC-V: define the elements of the VCSR vector CSR Heiko Stuebner
2023-03-01  2:22   ` Guo Ren
2023-03-15 18:31   ` Conor Dooley
2023-02-28 21:54 ` [PATCH RFC 2/2] RISC-V: add T-Head vector errata handling Heiko Stuebner
2023-03-01  2:12   ` Guo Ren
2023-03-15 18:56   ` Conor Dooley
2023-06-13  6:35   ` Stefan O'Rear
2023-06-22 17:39     ` Heiko Stübner
2023-06-22 18:58       ` Stefan O'Rear
2023-06-22 20:35         ` Heiko Stübner [this message]
2023-06-23  3:06           ` Stefan O'Rear
2023-06-23 10:22             ` Heiko Stübner
2023-06-23 23:26               ` Heiko Stübner
2023-06-24  3:23                 ` Stefan O'Rear
2023-06-23  9:12   ` Emil Renner Berthing
2023-03-01  2:21 ` [PATCH RFC 0/2] RISC-V: T-Head vector handling Guo Ren
2023-03-15  5:29 ` Palmer Dabbelt
2023-03-15  6:31   ` Heiko Stuebner
2023-06-12 15:29   ` Palmer Dabbelt
2023-06-12 15:44     ` Heiko Stübner

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