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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id s21-20020a056512203500b004ab98cd5644sm289679lfs.182.2022.11.30.07.19.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Nov 2022 07:19:07 -0800 (PST) Message-ID: <9183bac6-121e-0027-a88b-d77d5c9a077e@linaro.org> Date: Wed, 30 Nov 2022 16:19:06 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH v2 09/14] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Content-Language: en-US To: Hal Feng Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Conor Dooley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , Michael Turquette , Philipp Zabel , Emil Renner Berthing , linux-kernel@vger.kernel.org References: <20221118010627.70576-1-hal.feng@starfivetech.com> <20221118010627.70576-10-hal.feng@starfivetech.com> <1d62f95f-0edc-afd4-abb4-37fadc0b6a47@linaro.org> <72b3d10e-5a8e-ed42-6808-f53773913422@starfivetech.com> <768c2add-4c1f-0b36-5709-dbcdd560f504@starfivetech.com> <1fb1474b-ec13-e83a-973e-bd9e9a86cb44@linaro.org> <98d1bac7-8af5-f481-59b2-d58ca4c228ee@starfivetech.com> From: Krzysztof Kozlowski In-Reply-To: <98d1bac7-8af5-f481-59b2-d58ca4c228ee@starfivetech.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221130_071912_188610_38CB2932 X-CRM114-Status: GOOD ( 14.51 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 30/11/2022 16:12, Hal Feng wrote: > On Wed, 30 Nov 2022 12:48:30 +0100, Krzysztof Kozlowski wrote: >> On 30/11/2022 10:47, Hal Feng wrote: >>> On Fri, 25 Nov 2022 14:41:12 +0800, Hal Feng wrote: >>>> On Mon, 21 Nov 2022 09:47:08 +0100, Krzysztof Kozlowski wrote: >>>>> On 18/11/2022 02:06, Hal Feng wrote: >>>>>> From: Emil Renner Berthing >>>>>> >>>>>> Add bindings for the system clock and reset generator (SYSCRG) on the >>>>>> JH7110 RISC-V SoC by StarFive Ltd. >>>>>> >>>>>> Signed-off-by: Emil Renner Berthing >>>>>> Signed-off-by: Hal Feng >>>>> >>>>> Binding headers are coming with the file bringing bindings for the >>>>> device, so you need to squash patches. >>>> >>>> As we discussed in patch 7, could I merge patch 7, 8, 9, 10 and add the >>>> following files in one commit? >>>> >>>> include/dt-bindings/clock/starfive,jh7110-crg.h >>>> include/dt-bindings/reset/starfive,jh7110-crg.h >>>> Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >>>> Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml >>> >>> Hi, Krzysztof, >>> >>> Could you please give me some suggestions? >> >> You can keep aon and sys split. First add one of them with their own >> headers. Then add second with their own defines. > > You mean split patch 7 and patch 8 into sys part and aon part > respectively? There are totally five regions (sys/aon/stg/isp/vout) > for clocks and resets in JH7110. If we do that, there will be 5 > headers for JH7110 in either clock or reset directory finally. Is > that OK if there are too many headers for just one SoC? Sorry, I lost the track of what patches you have. The comment was - bindings include both the doc and headers. You want to split some, some merge, sorry, no clue. I did not propose splitting headers... Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv