From: Atish Patra <atish.patra@linux.dev>
To: Paul Walmsley <pjw@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh@kernel.org>, Anup Patel <anup@brainfault.org>,
Namhyung Kim <namhyung@kernel.org>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Ian Rogers <irogers@google.com>, Will Deacon <will@kernel.org>,
James Clark <james.clark@linaro.org>,
linux-arm-kernel@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org,
Conor Dooley <conor@kernel.org>
Subject: Re: [PATCH v8 05/22] RISC-V: Define indirect CSR access helpers
Date: Wed, 5 Aug 2026 00:59:45 -0700 [thread overview]
Message-ID: <920aee80-5297-4d70-a1ea-616976db7f70@linux.dev> (raw)
In-Reply-To: <1b20aa77-0f0f-08c7-9439-972983adf709@kernel.org>
On 8/4/26 5:39 PM, Paul Walmsley wrote:
> On Wed, 1 Jul 2026, Atish Patra wrote:
>
>> From: Atish Patra <atishp@rivosinc.com>
>>
>> The indirect CSR requires multiple instructions to read/write CSR.
>> Add a few helper functions for ease of usage.
>>
>> Signed-off-by: Atish Patra <atishp@rivosinc.com>
>
> Thanks. These macros seem better implemented as static inline functions.
> That also nicely aligns the code with what you write in the patch
> description.
I don't think inlining these macros in the following way will work
because of the following reason. It won't build once anything calls it.
csr_read()/csr_write() stringify the CSR argument straight into the
inline asm template:
#define csr_read(csr) \
({ \
register unsigned long __v; \
__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
: "=r" (__v) : \
: "memory"); \
__v; \
})
so the CSR operand has to be a literal token. With iregcsr as a function
parameter the template becomes "csrr %0, iregcsr", which will result in
the following compilation error
Error: unknown CSR `iregcsr'
The patch description should be fixed to indicate that these are macros.>
> Also, I renamed this file to change the abbreviation "ind" to "indirect",
> along the lines of this feedback here:
>
> https://lore.kernel.org/linux-riscv/CAHk-=whhSLGZAx3N5jJpb4GLFDqH_QvS07D+6BnkPWmCEzTAgw@mail.gmail.com/
>
> This case is even worse since there are already uses of "csr_index" in
> the codebase, so it's even more unclear what "ind" is supposed to mean.
>
Agreed on the expanding the abbreviation part and we should change it.
> Updated patch follows. Please let me know if you have any objections,
>
>
> - Paul
>
> From: Atish Patra <atishp@rivosinc.com>
>
> RISC-V: Define indirect CSR access helpers
>
> The indirect CSR requires multiple instructions to read/write CSR.
> Add a few helper functions for ease of usage.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
> Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
> Link: https://patch.msgid.link/20260701-counter_delegation-v8-5-7909f863a645@meta.com
> [pjw@kernel.org: expand "ind" abbreviation; use static inline functions rather than macros]
> Signed-off-by: Paul Walmsley <pjw@kernel.org>
> ---
> arch/riscv/include/asm/csr_indirect.h | 51 +++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 arch/riscv/include/asm/csr_indirect.h
>
> diff --git a/arch/riscv/include/asm/csr_indirect.h b/arch/riscv/include/asm/csr_indirect.h
> new file mode 100644
> index 000000000000..3cd6a9059455
> --- /dev/null
> +++ b/arch/riscv/include/asm/csr_indirect.h
> @@ -0,0 +1,51 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef _ASM_RISCV_CSR_INDIRECT_H
> +#define _ASM_RISCV_CSR_INDIRECT_H
> +
> +#include <linux/types.h>
> +#include <linux/irqflags.h>
> +
> +#include <asm/csr.h>
> +
> +static inline unsigned long csr_indirect_read(u16 iregcsr, u32 iselbase, u32 iseloff)
> +{
> + unsigned long __value = 0;
> + unsigned long __flags;
> +
> + local_irq_save(__flags);
> + csr_write(CSR_ISELECT, iselbase + iseloff);
> + __value = csr_read(iregcsr);
> + local_irq_restore(__flags);
> +
> + return __value;
> +}
> +
> +static inline void csr_indirect_write(u16 iregcsr, u32 iselbase, u32 iseloff, unsigned long value)
> +{
> + unsigned long __flags;
> +
> + local_irq_save(__flags);
> + csr_write(CSR_ISELECT, iselbase + iseloff);
> + csr_write(iregcsr, (value));
> + local_irq_restore(__flags);
> +}
> +
> +static inline unsigned long csr_indirect_warl(u16 iregcsr, u32 iselbase, u32 iseloff,
> + unsigned long warl_val)
> +{
> + unsigned long __old_val = 0, __value = 0;
> + unsigned long __flags;
> +
> + local_irq_save(__flags);
> + csr_write(CSR_ISELECT, iselbase + iseloff);
> + __old_val = csr_read(iregcsr);
> + csr_write(iregcsr, warl_val);
> + __value = csr_read(iregcsr);
> + csr_write(iregcsr, __old_val);
> + local_irq_restore(__flags);
> +
> + return __value;
> +}
> +
> +#endif
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next prev parent reply other threads:[~2026-08-05 8:00 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-01 8:46 [PATCH v8 00/22] Add Counter delegation ISA extension support Atish Patra
2026-07-01 8:46 ` [PATCH v8 01/22] RISC-V: perf: fix resource cleanup on driver probe failure Atish Patra
2026-07-20 7:21 ` Charlie Jenkins
2026-08-04 23:25 ` Paul Walmsley
2026-07-01 8:46 ` [PATCH v8 02/22] RISC-V: Add Sxcsrind ISA extension CSR definitions Atish Patra
2026-07-20 7:21 ` Charlie Jenkins
2026-08-04 23:35 ` Paul Walmsley
2026-08-04 23:42 ` Paul Walmsley
2026-08-05 7:30 ` Atish Patra
2026-07-01 8:46 ` [PATCH v8 03/22] RISC-V: Add Sxcsrind ISA extension definition and parsing Atish Patra
2026-07-20 7:21 ` Charlie Jenkins
2026-08-04 23:58 ` Paul Walmsley
2026-07-01 8:46 ` [PATCH v8 04/22] dt-bindings: riscv: add Sxcsrind ISA extension description Atish Patra
2026-08-05 0:29 ` Paul Walmsley
2026-07-01 8:46 ` [PATCH v8 05/22] RISC-V: Define indirect CSR access helpers Atish Patra
2026-07-20 7:21 ` Charlie Jenkins
2026-08-05 0:39 ` Paul Walmsley
2026-08-05 7:59 ` Atish Patra [this message]
2026-08-05 8:07 ` Atish Patra
2026-07-01 8:46 ` [PATCH v8 06/22] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2026-07-20 7:21 ` Charlie Jenkins
2026-08-05 0:44 ` Paul Walmsley
2026-07-01 8:46 ` [PATCH v8 07/22] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2026-08-05 0:44 ` Paul Walmsley
2026-07-01 8:46 ` [PATCH v8 08/22] RISC-V: Add Sscfg extension CSR definition Atish Patra
2026-07-20 7:21 ` Charlie Jenkins
2026-08-05 0:43 ` Paul Walmsley
2026-07-01 8:46 ` [PATCH v8 09/22] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing Atish Patra
2026-07-20 7:21 ` Charlie Jenkins
2026-08-05 0:46 ` Paul Walmsley
2026-07-01 8:46 ` [PATCH v8 10/22] dt-bindings: riscv: add Counter delegation ISA extensions description Atish Patra
2026-08-05 0:48 ` Paul Walmsley
2026-07-01 8:46 ` [PATCH v8 11/22] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2026-08-05 2:29 ` Paul Walmsley
2026-08-05 8:26 ` Atish Patra
2026-07-01 8:47 ` [PATCH v8 12/22] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2026-07-07 7:45 ` Yicong Yang
2026-08-05 8:46 ` Atish Patra
2026-07-20 7:21 ` Charlie Jenkins
2026-07-01 8:47 ` [PATCH v8 13/22] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2026-07-07 7:51 ` Yicong Yang
2026-08-03 21:53 ` Atish Patra
2026-07-20 7:21 ` Charlie Jenkins
2026-07-01 8:47 ` [PATCH v8 14/22] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2026-07-07 8:24 ` Yicong Yang
2026-08-06 2:00 ` Atish Patra
2026-08-06 12:16 ` Yicong Yang
2026-08-06 21:45 ` Atish Patra
2026-07-20 7:21 ` Charlie Jenkins
2026-07-01 8:47 ` [PATCH v8 15/22] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2026-07-01 8:47 ` [PATCH v8 16/22] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2026-07-20 7:21 ` Charlie Jenkins
2026-07-01 8:47 ` [PATCH v8 17/22] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2026-07-20 7:21 ` Charlie Jenkins
2026-07-01 8:47 ` [PATCH v8 18/22] RISC-V: perf: Add Qemu virt machine events Atish Patra
2026-07-20 7:21 ` Charlie Jenkins
2026-07-01 8:47 ` [PATCH v8 19/22] tools/perf: Support event code for arch standard events Atish Patra
2026-07-01 17:44 ` Ian Rogers
2026-07-01 8:47 ` [PATCH v8 20/22] tools/perf: Add RISC-V CounterIDMask event field Atish Patra
2026-07-01 17:44 ` Ian Rogers
2026-07-01 8:47 ` [PATCH v8 21/22] TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing Atish Patra
2026-07-01 8:47 ` [PATCH v8 22/22] TEST(do-not-upstream): fake qemu vendor JSON + mapfile entry for CounterIDMask path Atish Patra
2026-08-05 1:00 ` [PATCH v8 00/22] Add Counter delegation ISA extension support patchwork-bot+linux-riscv
2026-08-05 2:14 ` Paul Walmsley
2026-08-05 8:03 ` Atish Patra
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