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Mon, 16 Mar 2026 14:17:40 -0700 (PDT) Received: from [172.16.0.242] ([192.19.161.250]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2beab3e4a54sm18177198eec.10.2026.03.16.14.17.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Mar 2026 14:17:38 -0700 (PDT) Message-ID: <9bec308b-0f69-4515-91ce-a2e517d47be4@gmail.com> Date: Mon, 16 Mar 2026 14:22:54 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 1/6] riscv: Add a custom, simplified version of Svpbmt "XPbmtUC" To: Conor Dooley , Bo Gan Cc: linux-riscv@lists.infradead.org, samuel.holland@sifive.com, david@redhat.com, palmer@dabbelt.com, pjw@kernel.org, gaohan@iscas.ac.cn, me@ziyao.cc, lizhi2@eswincomputing.com, hal.feng@starfivetech.com, marcel@ziswiler.com, kernel@esmil.dk, devicetree@vger.kernel.org References: <20260313084407.29669-1-ganboing@gmail.com> <20260313084407.29669-2-ganboing@gmail.com> <20260313-visitor-majestic-1a6888dc57b2@spud> <25a8565d-a6bb-401f-b776-d743a2ec9ee0@gmail.com> <20260313-spiny-duration-702fff6bca17@spud> <20260314-errant-gnarly-dcca92457051@spud> <9592ecf2-8410-4df7-9b2c-17564426240d@gmail.com> <20260314-subdued-morally-f20a84fd446c@spud> Content-Language: en-US From: Bo Gan In-Reply-To: <20260314-subdued-morally-f20a84fd446c@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260316_141741_143948_C480F384 X-CRM114-Status: GOOD ( 21.33 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 3/14/26 05:17, Conor Dooley wrote: > On Fri, Mar 13, 2026 at 10:06:42PM -0700, Bo Gan wrote: >>> To be honest, I'm not completely dead-set opposed to a property that has >>> the bit positioning, but any property being added for what is >>> effectively an erratum needs to pass a high bar when the info could be >>> gathered in another way. That the eic7700 one depends on firmware for >>> what the bit may be is points in your favour, since firmware variability >>> is part of what dt is there to do. The jh7110 is points against, since >>> it could be fished out of the errata handling code. >>> >> Even for JH7110, I don't think it can be handled through the errata. It >> describes the errata of the core (if I'm not mistaken), and there can be >> other SoCs using the same core with the same archid/impid, but maps the >> peripherals differently, and the UC bit position doesn't apply there. I >> think you are probably looking for "SoC level errata" handling. It's not >> there AFAIK. Hence I guess both SoC cases point in favor of the dt prop? > > I dunno, nothing wrong with checking the devicetree during the errata > "probe" code. Checks are not limited to imp/arch ids, can do ecalls etc > etc in there too, so looking at the root compatible would be possible. > > Either way, if people like what you've done here generally (because > coming up with our own use of PTE bits could be controversial), and a > custom property of some sort is to be used, you need to provide a good > justification of why it is needed in the commit messages because you're > setting a precedent of being the first "extension" conjured up to suit > linux that would need that kind of functionality. > Need to demonstrate that it describes an aspect of the hardware, and > isn't being conjured up to configure software to use one out of several > possible values, that it may even be able to determine heuristically > from information already provided in the devicetree (like the root > compatible or a completely described memory node). Got your point. I've moved away from DT and "extension" in v2 and made it a sifive "errata", given that mapping memory twice through front/sys port is more of a sifive concept, not something generic to other core vendors. The DT is kept untouched, and the detection logic is done by a LUT and sbi ecalls if not predefined. Link: https://lore.kernel.org/linux-riscv/20260316060328.1173634-1-ganboing@gmail.com Bo _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv