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Wed, 23 Jul 2025 16:50:08 +0000 From: Matt Coster To: Michal Wilczynski , Krzysztof Kozlowski CC: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , Krzysztof Kozlowski , Bartosz Golaszewski , "linux-riscv@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "dri-devel@lists.freedesktop.org" Subject: Re: [PATCH v6 5/8] dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU compatible Thread-Topic: [PATCH v6 5/8] dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU compatible Thread-Index: AQHb+/HY3yjK/tPz4UisMcpCn+Norw== Date: Wed, 23 Jul 2025 16:50:08 +0000 Message-ID: <9c4f962d-6877-4a53-b0f3-218930f94e1e@imgtec.com> References: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> <20250623-apr_14_for_sending-v6-5-6583ce0f6c25@samsung.com> <9c82a6bc-c6ff-4656-8f60-9d5fa499b61a@imgtec.com> <27068fd3-92b5-402b-9f3c-fd786db56668@kernel.org> <491b69ce-5a2f-4df1-95af-9318bbe6c9b0@samsung.com> In-Reply-To: <491b69ce-5a2f-4df1-95af-9318bbe6c9b0@samsung.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: CWXP265MB3397:EE_|LO4P265MB6233:EE_ x-ms-office365-filtering-correlation-id: 27704dd4-980f-4eb7-01ed-08ddca08fb5f x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|366016|4053099003|38070700018; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============2076999940575356859==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============2076999940575356859== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------dXE0PDKVknsoEtR4e6oTSdv5" --------------dXE0PDKVknsoEtR4e6oTSdv5 Content-Type: multipart/mixed; boundary="------------KIDoU6Hyq0NyMaoFf7FlrZKt"; protected-headers="v1" From: Matt Coster To: Michal Wilczynski , Krzysztof Kozlowski Cc: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , Krzysztof Kozlowski , Bartosz Golaszewski , "linux-riscv@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "dri-devel@lists.freedesktop.org" Message-ID: <9c4f962d-6877-4a53-b0f3-218930f94e1e@imgtec.com> Subject: Re: [PATCH v6 5/8] dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU compatible References: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> <20250623-apr_14_for_sending-v6-5-6583ce0f6c25@samsung.com> <9c82a6bc-c6ff-4656-8f60-9d5fa499b61a@imgtec.com> <27068fd3-92b5-402b-9f3c-fd786db56668@kernel.org> <491b69ce-5a2f-4df1-95af-9318bbe6c9b0@samsung.com> In-Reply-To: <491b69ce-5a2f-4df1-95af-9318bbe6c9b0@samsung.com> --------------KIDoU6Hyq0NyMaoFf7FlrZKt Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On 23/07/2025 17:26, Michal Wilczynski wrote: > On 7/23/25 11:45, Matt Coster wrote: >> On 25/06/2025 15:41, Krzysztof Kozlowski wrote: >>> On 25/06/2025 16:18, Michal Wilczynski wrote: >>>> >>>> >>>> On 6/25/25 15:55, Krzysztof Kozlowski wrote: >>>>> On 25/06/2025 14:45, Michal Wilczynski wrote: >>>>>> >>>>>> >>>>>> On 6/24/25 15:53, Matt Coster wrote: >>>>>>> On 23/06/2025 12:42, Michal Wilczynski wrote: >>>>>>>> Update the img,powervr-rogue.yaml to include the T-HEAD TH1520 S= oC's >>>>>>>> specific GPU compatible string. >>>>>>>> >>>>>>>> The thead,th1520-gpu compatible, along with its full chain >>>>>>>> img,img-bxm-4-64, and img,img-rogue, is added to the >>>>>>>> list of recognized GPU types. >>>>>>>> >>>>>>>> The power-domains property requirement for img,img-bxm-4-64 is a= lso >>>>>>>> ensured by adding it to the relevant allOf condition. >>>>>>>> >>>>>>>> Acked-by: Krzysztof Kozlowski >>>>>>>> Reviewed-by: Ulf Hansson >>>>>>>> Reviewed-by: Bartosz Golaszewski >>>>>>>> Signed-off-by: Michal Wilczynski >>>>>>>> --- >>>>>>>> Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | = 9 ++++++++- >>>>>>>> 1 file changed, 8 insertions(+), 1 deletion(-) >>>>>>>> >>>>>>>> diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-r= ogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml >>>>>>>> index 4450e2e73b3ccf74d29f0e31e2e6687d7cbe5d65..9b241a0c1f5941dc= 58a1e23970f6d3773d427c22 100644 >>>>>>>> --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.ya= ml >>>>>>>> +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.ya= ml >>>>>>>> @@ -21,6 +21,11 @@ properties: >>>>>>>> # work with newer dts. >>>>>>>> - const: img,img-axe >>>>>>>> - const: img,img-rogue >>>>>>>> + - items: >>>>>>>> + - enum: >>>>>>>> + - thead,th1520-gpu >>>>>>>> + - const: img,img-bxm-4-64 >>>>>>>> + - const: img,img-rogue >>>>>>>> - items: >>>>>>>> - enum: >>>>>>>> - ti,j721s2-gpu >>>>>>>> @@ -93,7 +98,9 @@ allOf: >>>>>>>> properties: >>>>>>>> compatible: >>>>>>>> contains: >>>>>>>> - const: img,img-axe-1-16m >>>>>>>> + enum: >>>>>>>> + - img,img-axe-1-16m >>>>>>>> + - img,img-bxm-4-64 >>>>>>> >>>>>>> This isn't right =E2=80=93 BXM-4-64 has two power domains like BX= S-4-64. I don't >>>>>>> really know what the right way to handle that in devicetree is gi= ven the >>>>>>> TH1520 appears to expose only a top-level domain for the entire G= PU, but >>>>>>> there are definitely two separate domains underneath that as far = as the >>>>>>> GPU is concerned (see the attached snippet from integration guide= ). >>>>>>> >>>>>>> Since power nodes are ref-counted anyway, do we just use the same= node >>>>>>> for both domains and let the driver up/down-count it twice? >>>>>> >>>>>> Hi Matt, >>>>>> >>>>>> Thanks for the very helpful insight. That's a great point, it seem= s the >>>>>> SoC's design presents a tricky case for the bindings. >>>>>> >>>>>> I see what you mean about potentially using the same power domain = node >>>>>> twice. My only hesitation is that it might be a bit unclear for so= meone >>>>>> reading the devicetree later. Perhaps another option could be to r= elax >>>>>> the constraint for this compatible? >>>>>> >>>>>> Krzysztof, we'd be grateful for your thoughts on how to best model= this >>>>>> situation. >>>>> >>>>> >>>>> It's your hardware, you should tell us, not me. I don't know how ma= ny >>>>> power domains you have there, but for sure it is not one AND two do= mains >>>>> the same time. It is either one or two, because power domains are n= ot >>>>> the same as regulator supplies. >>>> >>>> Hi Krzysztof, Matt, >>>> >>>> The img,bxm-4-64 GPU IP itself is designed with two separate power >>>> domains. The TH1520 SoC, which integrates this GPU, wires both of th= ese >>>> to a single OS controllable power gate (controlled via mailbox and E= 902 >>>> co-processor). >>> >>> This helps... and also sounds a lot like regulator supplies, not powe= r >>> domains. :/ >> >> Apologies for taking so long to get back to you with this, I wanted to= >> make sure I had the whole picture from our side before commenting agai= n. >> >> From the GPU side, a "typical" integration of BXM-4-64 would use two >> power domains. >> >> Typically, these domains exist in silicon, regardless of whether they >> are exposed to the host OS, because the SoC's power controller must ha= ve >> control over them. As part of normal operation, the GPU firmware (alwa= ys >> in domain "a" on Rogue) will request the power-up/down of the other >> domains, including during the initial boot sequence. This all happens >> transparently to the OS. The GPU block itself has no power gating at >> that level, it relies entirely on the SoC integration. >> >> However, it turns out (unknown to me until very recently) that this >> functionality is optional. The integrator can opt to forego the >> power-saving functionality afforded by firmware-controlled power gatin= g >> and just throw everything into a single domain, which appears to be >> what's happened here. >> >> My only remaining issue here, then, is the naming. Since this >> integration doesn't use discrete domains, saying it has one domain >> called "a" isn't correct*. We should either: >> >> - Drop the name altogether for this integration (and others like it >> that don't use the low-power functionality, if there are any), or >=20 > Hi Matt, >=20 > Thanks for the detailed explanation, that clears things up perfectly. I'm glad I could get to the bottom of this one, it was bothering me too! >=20 > I agree with your assessment. Dropping the power-domain-names property > for this integration seems like the cleanest solution. As you pointed > out, since the OS sees only a single, undifferentiated power domain, > giving it a name like "gpu" would be redundant. This approach correctly= > models the hardware without setting a potentially confusing precedent. That seems reasonable. I was very much on the fence for this one, so I'll happily go along with dropping the name altogether. Just to make sure I understand correctly, the change here would be to move "required: - power-domain-names" from "img,img-rogue" to every conditional block that constrains the number of domains? Can we add negative constraints in conditionals? Then we could add "power-domain-names: false" to the "thead,th1520-gpu" conditional block alongside "power-domains: maxItems: 1". >=20 > To follow through on this, I assume we'll need to adjust > pvr_power_domains_init() to handle nodes that don't have the > power-domain-names property. Does that sound right to you? You should get away without making any code changes here, since we already shortcut on "domain_count <=3D 1" to just allow the pm_runtime to= deal with the single (or missing) domain directly. If we ever start controlling the individual domains ourselves from the kernel (rather than just ensuring they all come on and off in the correct sequence), we can add checks/handling for the no-name case then. Cheers, Matt >=20 >> - Come up with a new domain name to signal this explicitly (perhaps >> simply "gpu")? Something that's unlikely to clash with the "real" >> names that are going to start appearing in the Volcanic bindings >> (where we finally ditched "a", "b", etc.). >> >> Cheers, >> Matt >> >> *Yes, I know that's what we said for the AXE-1-16M, but that tiny GPU = is >> the exception to the rule; AFAIK it's the only one we've ever produced= >> that truly has only one power domain. >> >>> >>>> >>>> This means a devicetree for the TH1520 can only ever provide one pow= er >>>> domain for the GPU. However, a generic binding for img,bxm-4-64 shou= ld >>> >>> If this was a supply, you would have two supplies. Anyway internal >>> wirings of GPU do not matter in such case and more important what the= >>> SoC has wired. And it has one power domain. >>> >>> >>>> account for a future SoC that might implement both power domains. >>>> >>>> That's why I proposed to relax the constraints on the img,bmx-4-64 G= PU. >>> >>> This should be constrained per each device, so 1 for you and 2 for >>> everyone else. >>> >>> Best regards, >>> Krzysztof >> >> >=20 > Best regards, --=20 Matt Coster E: matt.coster@imgtec.com --------------KIDoU6Hyq0NyMaoFf7FlrZKt-- --------------dXE0PDKVknsoEtR4e6oTSdv5 Content-Type: application/pgp-signature; name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wnsEABYIACMWIQS4qDmoJvwmKhjY+nN5vBnz2d5qsAUCaIESvwUDAAAAAAAKCRB5vBnz2d5qsB7c AP40Rq4/1Q3nnECslH5ueXKDlr3OeU4xkWYTaVkspXcglgEAnkaEUuNyALc1kBrslCWD2eF1vnce K47RHWa4SbX8Rwg= =LvfX -----END PGP SIGNATURE----- --------------dXE0PDKVknsoEtR4e6oTSdv5-- --===============2076999940575356859== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============2076999940575356859==--