[PATCH v2 0/2] Add specific RZ/Five cache compatible

[PATCH v2 0/2] Add specific RZ/Five cache compatible

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

v2: add "-ax45mp" to compatible string.

CC: Ben Zong-You Xie <ben717@andestech.com>
CC: Conor Dooley <conor@kernel.org>
CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
CC: Geert Uytterhoeven <geert+renesas@glider.be>
CC: Magnus Damm <magnus.damm@gmail.com>
CC: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-renesas-soc@vger.kernel.org
CC: linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE)

Conor Dooley (2):
  dt-bindings: cache: add specific RZ/Five compatible to ax45mp
  riscv: dts: renesas: add specific RZ/Five cache compatible

 .../devicetree/bindings/cache/andestech,ax45mp-cache.yaml     | 4 +++-
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi                   | 3 ++-
 2 files changed, 5 insertions(+), 2 deletions(-)

-- 
2.45.2


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[PATCH v2 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

When the binding was originally written, it was assumed that all
ax45mp-caches had the same properties etc. This has turned out to be
incorrect, as the QiLai SoC has a different number of cache-sets.

Add a specific compatible for the RZ/Five for property enforcement and
in case there turns out to be additional differences between these
implementations of the cache controller.

Acked-by: Ben Zong-You Xie <ben717@andestech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../devicetree/bindings/cache/andestech,ax45mp-cache.yaml     | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
index d2cbe49f4e15f..82668d327344e 100644
--- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
@@ -28,6 +28,7 @@ select:
 properties:
   compatible:
     items:
+      - const: renesas,r9a07g043f-ax45mp-cache
       - const: andestech,ax45mp-cache
       - const: cache
 
@@ -70,7 +71,8 @@ examples:
     #include <dt-bindings/interrupt-controller/irq.h>
 
     cache-controller@13400000 {
-        compatible = "andestech,ax45mp-cache", "cache";
+        compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
+                     "cache";
         reg = <0x13400000 0x100000>;
         interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
         cache-line-size = <64>;
-- 
2.45.2


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[PATCH v2 2/2] riscv: dts: renesas: add specific RZ/Five cache compatible

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

When the binding was originally written, it was assumed that all
ax45mp-caches had the same properties etc. This has turned out to be
incorrect, as the QiLai SoC has a different number of cache-sets.

Add a specific compatible for the RZ/Five for property enforcement and
in case there turns out to be additional differences between these
implementations of the cache controller.

Acked-by: Ben Zong-You Xie <ben717@andestech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index e0ddf8f602c79..a8bcb26f42700 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -143,7 +143,8 @@ plic: interrupt-controller@12c00000 {
 	};
 
 	l2cache: cache-controller@13400000 {
-		compatible = "andestech,ax45mp-cache", "cache";
+		compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
+			     "cache";
 		reg = <0x0 0x13400000 0x0 0x100000>;
 		interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
 		cache-size = <0x40000>;
-- 
2.45.2


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Re: [PATCH v2 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

[Geert Uytterhoeven]

On Mon, 12 May 2025 at 15:48, Conor Dooley <conor@kernel.org> wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> When the binding was originally written, it was assumed that all
> ax45mp-caches had the same properties etc. This has turned out to be
> incorrect, as the QiLai SoC has a different number of cache-sets.
>
> Add a specific compatible for the RZ/Five for property enforcement and
> in case there turns out to be additional differences between these
> implementations of the cache controller.
>
> Acked-by: Ben Zong-You Xie <ben717@andestech.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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Re: [PATCH v2 2/2] riscv: dts: renesas: add specific RZ/Five cache compatible

[Geert Uytterhoeven]

Hi Conor,

On Mon, 12 May 2025 at 15:48, Conor Dooley <conor@kernel.org> wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> When the binding was originally written, it was assumed that all
> ax45mp-caches had the same properties etc. This has turned out to be
> incorrect, as the QiLai SoC has a different number of cache-sets.
>
> Add a specific compatible for the RZ/Five for property enforcement and
> in case there turns out to be additional differences between these
> implementations of the cache controller.
>
> Acked-by: Ben Zong-You Xie <ben717@andestech.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Thanks for the update!

> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -143,7 +143,8 @@ plic: interrupt-controller@12c00000 {
>         };
>
>         l2cache: cache-controller@13400000 {
> -               compatible = "andestech,ax45mp-cache", "cache";
> +               compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
> +                            "cache";
>                 reg = <0x0 0x13400000 0x0 0x100000>;
>                 interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
>                 cache-size = <0x40000>;

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.16 if there are no objections.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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Re: [PATCH v2 2/2] riscv: dts: renesas: add specific RZ/Five cache compatible

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1610 bytes --]

On Mon, May 12, 2025 at 03:57:41PM +0200, Geert Uytterhoeven wrote:
> Hi Conor,
> 
> On Mon, 12 May 2025 at 15:48, Conor Dooley <conor@kernel.org> wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > When the binding was originally written, it was assumed that all
> > ax45mp-caches had the same properties etc. This has turned out to be
> > incorrect, as the QiLai SoC has a different number of cache-sets.
> >
> > Add a specific compatible for the RZ/Five for property enforcement and
> > in case there turns out to be additional differences between these
> > implementations of the cache controller.
> >
> > Acked-by: Ben Zong-You Xie <ben717@andestech.com>
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> 
> Thanks for the update!
> 
> > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > @@ -143,7 +143,8 @@ plic: interrupt-controller@12c00000 {
> >         };
> >
> >         l2cache: cache-controller@13400000 {
> > -               compatible = "andestech,ax45mp-cache", "cache";
> > +               compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
> > +                            "cache";
> >                 reg = <0x0 0x13400000 0x0 0x100000>;
> >                 interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
> >                 cache-size = <0x40000>;
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-devel for v6.16 if there are no objections.

I'll grab the binding then on that basis. :+1:

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Re: [PATCH v2 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

[Lad, Prabhakar]

On Mon, May 12, 2025 at 3:12 PM Conor Dooley <conor@kernel.org> wrote:
>
> From: Conor Dooley <conor.dooley@microchip.com>
>
> When the binding was originally written, it was assumed that all
> ax45mp-caches had the same properties etc. This has turned out to be
> incorrect, as the QiLai SoC has a different number of cache-sets.
>
> Add a specific compatible for the RZ/Five for property enforcement and
> in case there turns out to be additional differences between these
> implementations of the cache controller.
>
> Acked-by: Ben Zong-You Xie <ben717@andestech.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../devicetree/bindings/cache/andestech,ax45mp-cache.yaml     | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Cheers,
Prabhakar

> diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> index d2cbe49f4e15f..82668d327344e 100644
> --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> @@ -28,6 +28,7 @@ select:
>  properties:
>    compatible:
>      items:
> +      - const: renesas,r9a07g043f-ax45mp-cache
>        - const: andestech,ax45mp-cache
>        - const: cache
>
> @@ -70,7 +71,8 @@ examples:
>      #include <dt-bindings/interrupt-controller/irq.h>
>
>      cache-controller@13400000 {
> -        compatible = "andestech,ax45mp-cache", "cache";
> +        compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
> +                     "cache";
>          reg = <0x13400000 0x100000>;
>          interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
>          cache-line-size = <64>;
> --
> 2.45.2
>
>

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Re: [PATCH v2 2/2] riscv: dts: renesas: add specific RZ/Five cache compatible

[Lad, Prabhakar]

On Mon, May 12, 2025 at 2:48 PM Conor Dooley <conor@kernel.org> wrote:
>
> From: Conor Dooley <conor.dooley@microchip.com>
>
> When the binding was originally written, it was assumed that all
> ax45mp-caches had the same properties etc. This has turned out to be
> incorrect, as the QiLai SoC has a different number of cache-sets.
>
> Add a specific compatible for the RZ/Five for property enforcement and
> in case there turns out to be additional differences between these
> implementations of the cache controller.
>
> Acked-by: Ben Zong-You Xie <ben717@andestech.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Cheers,
Prabhakar

> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> index e0ddf8f602c79..a8bcb26f42700 100644
> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -143,7 +143,8 @@ plic: interrupt-controller@12c00000 {
>         };
>
>         l2cache: cache-controller@13400000 {
> -               compatible = "andestech,ax45mp-cache", "cache";
> +               compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
> +                            "cache";
>                 reg = <0x0 0x13400000 0x0 0x100000>;
>                 interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
>                 cache-size = <0x40000>;
> --
> 2.45.2
>
>

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