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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=pXVo7Cs71/tg5/xPQSHIws0jZdPnU8iJoGi0JM0s6PA=; b=RTWbmh2E/36cKer/eQqBqdxvqY5Jy6fDWr0ahElO2t5BfsZ9seHoB2FvDl6zYCLMom 7mSCDYzz2/PyVjVqpqPikkUDAN9MbpOpZM+naP5Zt5f0C1ochppUfYZqH+gHhjj7qky9 VHaPKHNz4Du6rEwyGvlSTAIo1a8A7rko3W1dGb/2bRU3XXHjoEzTfre1GhL6e+wfrWBE p/kWwSlb7fcZptv0AFehUW/aDJ16c6XqQO0ACy0l7LEpA3rI4j35ai7lALQ3ojVPXHyT Nne8EflQpJvx6QEMZhtzyx80/BEsGc9Ul6LdFQXQYC+xRej76wsG0DeKiMbFAzrHLRgi xlsA== X-Gm-Message-State: ACrzQf0lWS+Uirh5K1GMlEEpACNo5MD+iVmVOtN2l2KaEG8BRBoLyOwI 0QtoZz8LD76c3U8qC0xqPCI3TuMcwj2lN96xP9Y= X-Google-Smtp-Source: AMsMyM7xXJNCoERdhmhuTM7BqnBPmPnAjrk0xQutO5ohc44YQZYfyQ01mi7FS4e/VFr3sHX7diHSkNtWtFmGwWDXThY= X-Received: by 2002:a17:906:5a4e:b0:78c:8106:9cc1 with SMTP id my14-20020a1709065a4e00b0078c81069cc1mr9072279ejc.196.1664964889317; Wed, 05 Oct 2022 03:14:49 -0700 (PDT) MIME-Version: 1.0 References: <20221003223222.448551-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221003223222.448551-3-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Wed, 5 Oct 2022 11:14:22 +0100 Message-ID: Subject: Re: [RFC PATCH v2 2/2] soc: renesas: Add L2 cache management for RZ/Five SoC To: Arnd Bergmann Cc: Conor Dooley , Geert Uytterhoeven , Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Krzysztof Kozlowski , Magnus Damm , =?UTF-8?Q?Heiko_St=C3=BCbner?= , guoren , "Conor.Dooley" , Philipp Tomsich , Nathan Chancellor , Atish Patra , Anup Patel , Linux-Renesas , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Biju Das , "Lad, Prabhakar" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221005_031453_084723_0129A3C7 X-CRM114-Status: GOOD ( 18.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Arnd, On Wed, Oct 5, 2022 at 10:58 AM Arnd Bergmann wrote: > > On Tue, Oct 4, 2022, at 7:42 PM, Conor Dooley wrote: > > On Mon, Oct 03, 2022 at 11:32:22PM +0100, Prabhakar wrote: > >> > >> Signed-off-by: Lad Prabhakar > >> --- > >> arch/riscv/include/asm/cacheflush.h | 8 + > >> arch/riscv/include/asm/errata_list.h | 2 + > >> arch/riscv/include/asm/sbi.h | 1 + > >> arch/riscv/mm/dma-noncoherent.c | 20 ++ > > > > Stupid question maybe, but I assume you mixed the driver addition and > > the changes to arch/riscv for the sake of easily creating the RFC? > > > >> drivers/soc/renesas/Makefile | 4 + > >> drivers/soc/renesas/rzf/Makefile | 3 + > >> drivers/soc/renesas/rzf/ax45mp_cache.c | 365 +++++++++++++++++++++++++ > >> drivers/soc/renesas/rzf/rzf_sbi.h | 27 ++ > > My feeling is that L2 cache behavior should live in arch/riscv > rather than drivers/soc/, since this is not specific to a SoC > family but rather the CPU core. I would also expect that the > actual implementation and DT binding can be shared with > non-renesas SoCs using the same CPU core. > Totally agree it is related to the CPU core and not the SoC. During the BoF session it was agreed that unratified extensions code shouldnt go under the arch/riscv. Since the code has vendor specific SBI calls RISC-V maintainers asked to move it SoC specific so that maintenance of the code falls under SoC vendors. Cheers, Prabhakar _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv