* [PATCH V8 0/3] riscv: mm: Add soft-dirty and uffd-wp support
@ 2025-06-19 6:52 Chunyan Zhang
2025-06-19 6:52 ` [PATCH V8 1/3] riscv: Add RISC-V Svrsw60t59b extension support Chunyan Zhang
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Chunyan Zhang @ 2025-06-19 6:52 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Andrew Morton
Cc: linux-riscv, Deepak Gupta, Ved Shanbhogue, linux-kernel,
Chunyan Zhang
This patchset adds Svrsw60t59b [1] extension support, also soft dirty and userfaultfd
write protect tracking for RISC-V.
This patchset has been tested with kselftest mm suite in which soft-dirty,
madv_populate, test_unmerge_uffd_wp, and uffd-unit-tests run and pass,
and no regressions are observed in any of the other tests.
This patchset applies on top of v6.16-rc1.
V8:
- Rebase on v6.16-rc1;
- Add dependencies to MMU && 64BIT for RISCV_ISA_SVRSW60T59B;
- Use 'Svrsw60t59b' instead of 'SVRSW60T59B' in Kconfig help paragraph;
- Add Alex's Reviewed-by tag in patch 1.
V7: (https://lore.kernel.org/all/20250409095320.224100-1-zhangchunyan@iscas.ac.cn/)
- Add Svrsw60t59b [1] extension support;
- Have soft-dirty and uffd-wp depending on the Svrsw60t59b extension to
avoid crashes for the hardware which don't have this extension.
V6:
- Changes to use bits 59-60 which are supported by extension Svrsw60t59b
for soft dirty and userfaultfd write protect tracking.
V5:
- Fixed typos and corrected some words in Kconfig and commit message;
- Removed pte_wrprotect() from pte_swp_mkuffd_wp(), this is a copy-paste
error;
- Added Alex's Reviewed-by tag in patch 2.
V4:
- Added bit(4) descriptions into "Format of swap PTE".
V3:
- Fixed the issue reported by kernel test irobot <lkp@intel.com>.
V1 -> V2:
- Add uffd-wp supported;
- Make soft-dirty uffd-wp and devmap mutually exclusive which all use
the same PTE bit;
- Add test results of CRIU in the cover-letter.
[1] https://github.com/riscv/Svrsw60t59b.git
Chunyan Zhang (3):
riscv: Add RISC-V Svrsw60t59b extension support
riscv: mm: Add soft-dirty page tracking support
riscv: mm: Add uffd write-protect support
arch/riscv/Kconfig | 16 +++
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/pgtable-bits.h | 37 +++++++
arch/riscv/include/asm/pgtable.h | 136 +++++++++++++++++++++++++-
arch/riscv/kernel/cpufeature.c | 1 +
5 files changed, 189 insertions(+), 2 deletions(-)
--
2.34.1
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH V8 1/3] riscv: Add RISC-V Svrsw60t59b extension support
2025-06-19 6:52 [PATCH V8 0/3] riscv: mm: Add soft-dirty and uffd-wp support Chunyan Zhang
@ 2025-06-19 6:52 ` Chunyan Zhang
2025-06-19 6:52 ` [PATCH V8 2/3] riscv: mm: Add soft-dirty page tracking support Chunyan Zhang
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Chunyan Zhang @ 2025-06-19 6:52 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Andrew Morton
Cc: linux-riscv, Deepak Gupta, Ved Shanbhogue, linux-kernel,
Chunyan Zhang
The Svrsw60t59b extension allows to free the PTE reserved bits 60
and 59 for software to use.
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
---
arch/riscv/Kconfig | 14 ++++++++++++++
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
3 files changed, 16 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 36061f4732b7..01e4c15bee12 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -864,6 +864,20 @@ config RISCV_ISA_ZICBOP
If you don't know what to do here, say Y.
+config RISCV_ISA_SVRSW60T59B
+ bool "Svrsw60t59b extension support for using PTE bits 60 and 59"
+ depends on MMU && 64BIT
+ depends on RISCV_ALTERNATIVE
+ default y
+ help
+ Adds support to dynamically detect the presence of the Svrsw60t59b
+ extension and enable its usage.
+
+ The Svrsw60t59b extension allows to free the PTE reserved bits 60
+ and 59 for software to use.
+
+ If you don't know what to do here, say Y.
+
config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
def_bool y
# https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index affd63e11b0a..f98fcb5c17d5 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -106,6 +106,7 @@
#define RISCV_ISA_EXT_ZAAMO 97
#define RISCV_ISA_EXT_ZALRSC 98
#define RISCV_ISA_EXT_ZICBOP 99
+#define RISCV_ISA_EXT_SVRSW60T59B 100
#define RISCV_ISA_EXT_XLINUXENVCFG 127
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 743d53415572..de29562096ff 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -540,6 +540,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
__RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),
+ __RISCV_ISA_EXT_DATA(svrsw60t59b, RISCV_ISA_EXT_SVRSW60T59B),
};
const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
--
2.34.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH V8 2/3] riscv: mm: Add soft-dirty page tracking support
2025-06-19 6:52 [PATCH V8 0/3] riscv: mm: Add soft-dirty and uffd-wp support Chunyan Zhang
2025-06-19 6:52 ` [PATCH V8 1/3] riscv: Add RISC-V Svrsw60t59b extension support Chunyan Zhang
@ 2025-06-19 6:52 ` Chunyan Zhang
2025-06-23 23:19 ` Palmer Dabbelt
2025-06-19 6:52 ` [PATCH V8 3/3] riscv: mm: Add uffd write-protect support Chunyan Zhang
` (2 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Chunyan Zhang @ 2025-06-19 6:52 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Andrew Morton
Cc: linux-riscv, Deepak Gupta, Ved Shanbhogue, linux-kernel,
Chunyan Zhang
The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software, this patch uses bit 59 for soft-dirty.
To add swap PTE soft-dirty tracking, we borrow bit 3 which is available
for swap PTEs on RISC-V systems.
Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/pgtable-bits.h | 19 +++++++
arch/riscv/include/asm/pgtable.h | 71 ++++++++++++++++++++++++++-
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 01e4c15bee12..5c787c09f4dc 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -141,6 +141,7 @@ config RISCV
select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
select HAVE_ARCH_SECCOMP_FILTER
+ select HAVE_ARCH_SOFT_DIRTY if 64BIT && MMU && RISCV_ISA_SVRSW60T59B
select HAVE_ARCH_STACKLEAK
select HAVE_ARCH_THREAD_STRUCT_WHITELIST
select HAVE_ARCH_TRACEHOOK
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index a8f5205cea54..a6fa871dc19e 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -20,6 +20,25 @@
#define _PAGE_SPECIAL (1 << 8) /* RSW: 0x1 */
#define _PAGE_DEVMAP (1 << 9) /* RSW, devmap */
+
+#ifdef CONFIG_MEM_SOFT_DIRTY
+
+/* ext_svrsw60t59b: bit 59 for software dirty tracking */
+#define _PAGE_SOFT_DIRTY \
+ ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ? \
+ (1UL << 59) : 0)
+/*
+ * Bit 3 is always zero for swap entry computation, so we
+ * can borrow it for swap page soft-dirty tracking.
+ */
+#define _PAGE_SWP_SOFT_DIRTY \
+ ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ? \
+ _PAGE_EXEC : 0)
+#else
+#define _PAGE_SOFT_DIRTY 0
+#define _PAGE_SWP_SOFT_DIRTY 0
+#endif /* CONFIG_MEM_SOFT_DIRTY */
+
#define _PAGE_TABLE _PAGE_PRESENT
/*
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index a11816bbf9e7..efc2da97f124 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -434,7 +434,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
static inline pte_t pte_mkdirty(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_DIRTY);
+ return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
}
static inline pte_t pte_mkclean(pte_t pte)
@@ -467,6 +467,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
return pte;
}
+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
+static inline bool pte_soft_dirty(pte_t pte)
+{
+ return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
+}
+
+static inline pte_t pte_mksoft_dirty(pte_t pte)
+{
+ return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
+}
+
+static inline pte_t pte_clear_soft_dirty(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
+}
+
+static inline bool pte_swp_soft_dirty(pte_t pte)
+{
+ return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY);
+}
+
+static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
+{
+ return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
+}
+
+static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
+}
+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
+
#ifdef CONFIG_RISCV_ISA_SVNAPOT
#define pte_leaf_size(pte) (pte_napot(pte) ? \
napot_cont_size(napot_cont_order(pte)) :\
@@ -819,6 +851,40 @@ static inline pud_t pud_mkspecial(pud_t pud)
}
#endif
+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
+static inline bool pmd_soft_dirty(pmd_t pmd)
+{
+ return pte_soft_dirty(pmd_pte(pmd));
+}
+
+static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
+{
+ return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
+}
+
+static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
+{
+ return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
+}
+
+#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
+static inline bool pmd_swp_soft_dirty(pmd_t pmd)
+{
+ return pte_swp_soft_dirty(pmd_pte(pmd));
+}
+
+static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
+{
+ return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
+}
+
+static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
+{
+ return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
+}
+#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
+
static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
pmd_t *pmdp, pmd_t pmd)
{
@@ -1005,7 +1071,8 @@ static inline pud_t pud_modify(pud_t pud, pgprot_t newprot)
*
* Format of swap PTE:
* bit 0: _PAGE_PRESENT (zero)
- * bit 1 to 3: _PAGE_LEAF (zero)
+ * bit 1 to 2: (zero)
+ * bit 3: _PAGE_SWP_SOFT_DIRTY
* bit 5: _PAGE_PROT_NONE (zero)
* bit 6: exclusive marker
* bits 7 to 11: swap type
--
2.34.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH V8 3/3] riscv: mm: Add uffd write-protect support
2025-06-19 6:52 [PATCH V8 0/3] riscv: mm: Add soft-dirty and uffd-wp support Chunyan Zhang
2025-06-19 6:52 ` [PATCH V8 1/3] riscv: Add RISC-V Svrsw60t59b extension support Chunyan Zhang
2025-06-19 6:52 ` [PATCH V8 2/3] riscv: mm: Add soft-dirty page tracking support Chunyan Zhang
@ 2025-06-19 6:52 ` Chunyan Zhang
2025-06-19 9:34 ` [PATCH V8 0/3] riscv: mm: Add soft-dirty and uffd-wp support Chunyan Zhang
2025-06-23 23:03 ` Palmer Dabbelt
4 siblings, 0 replies; 8+ messages in thread
From: Chunyan Zhang @ 2025-06-19 6:52 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Andrew Morton
Cc: linux-riscv, Deepak Gupta, Ved Shanbhogue, linux-kernel,
Chunyan Zhang
The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software, this patch uses bit 60 for uffd-wp tracking
Additionally for tracking the uffd-wp state as a PTE swap bit, we borrow
bit 4 which is not involved into swap entry computation.
Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/pgtable-bits.h | 18 ++++++++
arch/riscv/include/asm/pgtable.h | 65 +++++++++++++++++++++++++++
3 files changed, 84 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 5c787c09f4dc..2cc2b56c87a5 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -148,6 +148,7 @@ config RISCV
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT && MMU
select HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD if 64BIT && MMU
select HAVE_ARCH_USERFAULTFD_MINOR if 64BIT && USERFAULTFD
+ select HAVE_ARCH_USERFAULTFD_WP if 64BIT && MMU && USERFAULTFD && RISCV_ISA_SVRSW60T59B
select HAVE_ARCH_VMAP_STACK if MMU && 64BIT
select HAVE_ASM_MODVERSIONS
select HAVE_CONTEXT_TRACKING_USER
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index a6fa871dc19e..a953a582cd75 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -39,6 +39,24 @@
#define _PAGE_SWP_SOFT_DIRTY 0
#endif /* CONFIG_MEM_SOFT_DIRTY */
+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
+
+/* ext_svrsw60t59b: Bit(60) for uffd-wp tracking */
+#define _PAGE_UFFD_WP \
+ ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ? \
+ (1UL << 60) : 0)
+/*
+ * Bit 4 is not involved into swap entry computation, so we
+ * can borrow it for swap page uffd-wp tracking.
+ */
+#define _PAGE_SWP_UFFD_WP \
+ ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ? \
+ _PAGE_USER : 0)
+#else
+#define _PAGE_UFFD_WP 0
+#define _PAGE_SWP_UFFD_WP 0
+#endif
+
#define _PAGE_TABLE _PAGE_PRESENT
/*
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index efc2da97f124..9630d2b2d67e 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -423,6 +423,38 @@ static inline pte_t pte_wrprotect(pte_t pte)
return __pte(pte_val(pte) & ~(_PAGE_WRITE));
}
+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
+static inline bool pte_uffd_wp(pte_t pte)
+{
+ return !!(pte_val(pte) & _PAGE_UFFD_WP);
+}
+
+static inline pte_t pte_mkuffd_wp(pte_t pte)
+{
+ return pte_wrprotect(__pte(pte_val(pte) | _PAGE_UFFD_WP));
+}
+
+static inline pte_t pte_clear_uffd_wp(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~(_PAGE_UFFD_WP));
+}
+
+static inline bool pte_swp_uffd_wp(pte_t pte)
+{
+ return !!(pte_val(pte) & _PAGE_SWP_UFFD_WP);
+}
+
+static inline pte_t pte_swp_mkuffd_wp(pte_t pte)
+{
+ return __pte(pte_val(pte) | _PAGE_SWP_UFFD_WP);
+}
+
+static inline pte_t pte_swp_clear_uffd_wp(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~(_PAGE_SWP_UFFD_WP));
+}
+#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
+
/* static inline pte_t pte_mkread(pte_t pte) */
static inline pte_t pte_mkwrite_novma(pte_t pte)
@@ -851,6 +883,38 @@ static inline pud_t pud_mkspecial(pud_t pud)
}
#endif
+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
+static inline bool pmd_uffd_wp(pmd_t pmd)
+{
+ return pte_uffd_wp(pmd_pte(pmd));
+}
+
+static inline pmd_t pmd_mkuffd_wp(pmd_t pmd)
+{
+ return pte_pmd(pte_mkuffd_wp(pmd_pte(pmd)));
+}
+
+static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd)
+{
+ return pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd)));
+}
+
+static inline bool pmd_swp_uffd_wp(pmd_t pmd)
+{
+ return pte_swp_uffd_wp(pmd_pte(pmd));
+}
+
+static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd)
+{
+ return pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd)));
+}
+
+static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd)
+{
+ return pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd)));
+}
+#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
+
#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
static inline bool pmd_soft_dirty(pmd_t pmd)
{
@@ -1073,6 +1137,7 @@ static inline pud_t pud_modify(pud_t pud, pgprot_t newprot)
* bit 0: _PAGE_PRESENT (zero)
* bit 1 to 2: (zero)
* bit 3: _PAGE_SWP_SOFT_DIRTY
+ * bit 4: _PAGE_SWP_UFFD_WP
* bit 5: _PAGE_PROT_NONE (zero)
* bit 6: exclusive marker
* bits 7 to 11: swap type
--
2.34.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH V8 0/3] riscv: mm: Add soft-dirty and uffd-wp support
2025-06-19 6:52 [PATCH V8 0/3] riscv: mm: Add soft-dirty and uffd-wp support Chunyan Zhang
` (2 preceding siblings ...)
2025-06-19 6:52 ` [PATCH V8 3/3] riscv: mm: Add uffd write-protect support Chunyan Zhang
@ 2025-06-19 9:34 ` Chunyan Zhang
2025-06-23 23:03 ` Palmer Dabbelt
4 siblings, 0 replies; 8+ messages in thread
From: Chunyan Zhang @ 2025-06-19 9:34 UTC (permalink / raw)
To: Chunyan Zhang
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Andrew Morton, linux-riscv, Deepak Gupta, Ved Shanbhogue,
linux-kernel
On Thu, 19 Jun 2025 at 15:27, Chunyan Zhang <zhangchunyan@iscas.ac.cn> wrote:
>
> This patchset adds Svrsw60t59b [1] extension support, also soft dirty and userfaultfd
> write protect tracking for RISC-V.
>
> This patchset has been tested with kselftest mm suite in which soft-dirty,
> madv_populate, test_unmerge_uffd_wp, and uffd-unit-tests run and pass,
> and no regressions are observed in any of the other tests.
>
I also tried CRIU below functions and they can work fine with this patch:
- 'criu check --feature mem_dirty_track' returns supported
- The incremental_dumps works fine (https://www.criu.org/Incremental_dumps)
> This patchset applies on top of v6.16-rc1.
>
> V8:
> - Rebase on v6.16-rc1;
> - Add dependencies to MMU && 64BIT for RISCV_ISA_SVRSW60T59B;
> - Use 'Svrsw60t59b' instead of 'SVRSW60T59B' in Kconfig help paragraph;
> - Add Alex's Reviewed-by tag in patch 1.
>
> V7: (https://lore.kernel.org/all/20250409095320.224100-1-zhangchunyan@iscas.ac.cn/)
> - Add Svrsw60t59b [1] extension support;
> - Have soft-dirty and uffd-wp depending on the Svrsw60t59b extension to
> avoid crashes for the hardware which don't have this extension.
>
> V6:
> - Changes to use bits 59-60 which are supported by extension Svrsw60t59b
> for soft dirty and userfaultfd write protect tracking.
>
> V5:
> - Fixed typos and corrected some words in Kconfig and commit message;
> - Removed pte_wrprotect() from pte_swp_mkuffd_wp(), this is a copy-paste
> error;
> - Added Alex's Reviewed-by tag in patch 2.
>
> V4:
> - Added bit(4) descriptions into "Format of swap PTE".
>
> V3:
> - Fixed the issue reported by kernel test irobot <lkp@intel.com>.
>
> V1 -> V2:
> - Add uffd-wp supported;
> - Make soft-dirty uffd-wp and devmap mutually exclusive which all use
> the same PTE bit;
> - Add test results of CRIU in the cover-letter.
>
> [1] https://github.com/riscv/Svrsw60t59b.git
>
> Chunyan Zhang (3):
> riscv: Add RISC-V Svrsw60t59b extension support
> riscv: mm: Add soft-dirty page tracking support
> riscv: mm: Add uffd write-protect support
>
> arch/riscv/Kconfig | 16 +++
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/include/asm/pgtable-bits.h | 37 +++++++
> arch/riscv/include/asm/pgtable.h | 136 +++++++++++++++++++++++++-
> arch/riscv/kernel/cpufeature.c | 1 +
> 5 files changed, 189 insertions(+), 2 deletions(-)
>
> --
> 2.34.1
>
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V8 0/3] riscv: mm: Add soft-dirty and uffd-wp support
2025-06-19 6:52 [PATCH V8 0/3] riscv: mm: Add soft-dirty and uffd-wp support Chunyan Zhang
` (3 preceding siblings ...)
2025-06-19 9:34 ` [PATCH V8 0/3] riscv: mm: Add soft-dirty and uffd-wp support Chunyan Zhang
@ 2025-06-23 23:03 ` Palmer Dabbelt
2025-06-24 13:45 ` Ved Shanbhogue
4 siblings, 1 reply; 8+ messages in thread
From: Palmer Dabbelt @ 2025-06-23 23:03 UTC (permalink / raw)
To: zhangchunyan
Cc: Paul Walmsley, aou, Alexandre Ghiti, akpm, linux-riscv, debug,
Vedvyas Shanbhogue, linux-kernel, zhang.lyra
On Wed, 18 Jun 2025 23:52:29 PDT (-0700), zhangchunyan@iscas.ac.cn wrote:
> This patchset adds Svrsw60t59b [1] extension support, also soft dirty and userfaultfd
> write protect tracking for RISC-V.
>
> This patchset has been tested with kselftest mm suite in which soft-dirty,
> madv_populate, test_unmerge_uffd_wp, and uffd-unit-tests run and pass,
> and no regressions are observed in any of the other tests.
>
> This patchset applies on top of v6.16-rc1.
>
> V8:
> - Rebase on v6.16-rc1;
> - Add dependencies to MMU && 64BIT for RISCV_ISA_SVRSW60T59B;
> - Use 'Svrsw60t59b' instead of 'SVRSW60T59B' in Kconfig help paragraph;
> - Add Alex's Reviewed-by tag in patch 1.
>
> V7: (https://lore.kernel.org/all/20250409095320.224100-1-zhangchunyan@iscas.ac.cn/)
> - Add Svrsw60t59b [1] extension support;
> - Have soft-dirty and uffd-wp depending on the Svrsw60t59b extension to
> avoid crashes for the hardware which don't have this extension.
>
> V6:
> - Changes to use bits 59-60 which are supported by extension Svrsw60t59b
> for soft dirty and userfaultfd write protect tracking.
>
> V5:
> - Fixed typos and corrected some words in Kconfig and commit message;
> - Removed pte_wrprotect() from pte_swp_mkuffd_wp(), this is a copy-paste
> error;
> - Added Alex's Reviewed-by tag in patch 2.
>
> V4:
> - Added bit(4) descriptions into "Format of swap PTE".
>
> V3:
> - Fixed the issue reported by kernel test irobot <lkp@intel.com>.
>
> V1 -> V2:
> - Add uffd-wp supported;
> - Make soft-dirty uffd-wp and devmap mutually exclusive which all use
> the same PTE bit;
> - Add test results of CRIU in the cover-letter.
>
> [1] https://github.com/riscv/Svrsw60t59b.git
This 404s (with or without the ".git" suffix). I remember seeing the
spec at some point, but I can't find it anywhwere else.
>
> Chunyan Zhang (3):
> riscv: Add RISC-V Svrsw60t59b extension support
> riscv: mm: Add soft-dirty page tracking support
> riscv: mm: Add uffd write-protect support
>
> arch/riscv/Kconfig | 16 +++
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/include/asm/pgtable-bits.h | 37 +++++++
> arch/riscv/include/asm/pgtable.h | 136 +++++++++++++++++++++++++-
> arch/riscv/kernel/cpufeature.c | 1 +
> 5 files changed, 189 insertions(+), 2 deletions(-)
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V8 2/3] riscv: mm: Add soft-dirty page tracking support
2025-06-19 6:52 ` [PATCH V8 2/3] riscv: mm: Add soft-dirty page tracking support Chunyan Zhang
@ 2025-06-23 23:19 ` Palmer Dabbelt
0 siblings, 0 replies; 8+ messages in thread
From: Palmer Dabbelt @ 2025-06-23 23:19 UTC (permalink / raw)
To: zhangchunyan
Cc: Paul Walmsley, aou, Alexandre Ghiti, akpm, linux-riscv, debug,
Vedvyas Shanbhogue, linux-kernel, zhang.lyra
On Wed, 18 Jun 2025 23:52:31 PDT (-0700), zhangchunyan@iscas.ac.cn wrote:
> The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
> for software, this patch uses bit 59 for soft-dirty.
>
> To add swap PTE soft-dirty tracking, we borrow bit 3 which is available
> for swap PTEs on RISC-V systems.
>
> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> ---
> arch/riscv/Kconfig | 1 +
> arch/riscv/include/asm/pgtable-bits.h | 19 +++++++
> arch/riscv/include/asm/pgtable.h | 71 ++++++++++++++++++++++++++-
> 3 files changed, 89 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 01e4c15bee12..5c787c09f4dc 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -141,6 +141,7 @@ config RISCV
> select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
> select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
> select HAVE_ARCH_SECCOMP_FILTER
> + select HAVE_ARCH_SOFT_DIRTY if 64BIT && MMU && RISCV_ISA_SVRSW60T59B
> select HAVE_ARCH_STACKLEAK
> select HAVE_ARCH_THREAD_STRUCT_WHITELIST
> select HAVE_ARCH_TRACEHOOK
> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> index a8f5205cea54..a6fa871dc19e 100644
> --- a/arch/riscv/include/asm/pgtable-bits.h
> +++ b/arch/riscv/include/asm/pgtable-bits.h
> @@ -20,6 +20,25 @@
>
> #define _PAGE_SPECIAL (1 << 8) /* RSW: 0x1 */
> #define _PAGE_DEVMAP (1 << 9) /* RSW, devmap */
> +
> +#ifdef CONFIG_MEM_SOFT_DIRTY
> +
> +/* ext_svrsw60t59b: bit 59 for software dirty tracking */
> +#define _PAGE_SOFT_DIRTY \
> + ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ? \
> + (1UL << 59) : 0)
I haven't fully followed the code paths here, but it looks like we'll
unconditionally enable VM_SOFTDIRTY and thus allow
vma_soft_dirty_enabled() to return true even when we don't have support
in hardware.
I'm not exactly sure what could go wrong there, but it seems like at
least userspace could be told that soft dirty is around and thus get
confused. It also looks like debug_vm_pgtable() will start failing
tests on these systems, which will probably trigger some bug reports.
At a bare minimum someone who understands the core MM code should look
here. Maybe the best way to do that is to convert those static
CONFIG_MEM_SOFT_DIRTY checks to some sort of arch-implemented callback
so this can be dynamic, and then see what people say?
> +/*
> + * Bit 3 is always zero for swap entry computation, so we
> + * can borrow it for swap page soft-dirty tracking.
> + */
> +#define _PAGE_SWP_SOFT_DIRTY \
> + ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ? \
> + _PAGE_EXEC : 0)
> +#else
> +#define _PAGE_SOFT_DIRTY 0
> +#define _PAGE_SWP_SOFT_DIRTY 0
> +#endif /* CONFIG_MEM_SOFT_DIRTY */
> +
> #define _PAGE_TABLE _PAGE_PRESENT
>
> /*
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index a11816bbf9e7..efc2da97f124 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -434,7 +434,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
>
> static inline pte_t pte_mkdirty(pte_t pte)
> {
> - return __pte(pte_val(pte) | _PAGE_DIRTY);
> + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
> }
>
> static inline pte_t pte_mkclean(pte_t pte)
> @@ -467,6 +467,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
> return pte;
> }
>
> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> +static inline bool pte_soft_dirty(pte_t pte)
> +{
> + return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
> +}
> +
> +static inline pte_t pte_mksoft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
> +}
> +
> +static inline pte_t pte_clear_soft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
> +}
> +
> +static inline bool pte_swp_soft_dirty(pte_t pte)
> +{
> + return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY);
> +}
> +
> +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
> +}
> +
> +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
> +}
> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> +
> #ifdef CONFIG_RISCV_ISA_SVNAPOT
> #define pte_leaf_size(pte) (pte_napot(pte) ? \
> napot_cont_size(napot_cont_order(pte)) :\
> @@ -819,6 +851,40 @@ static inline pud_t pud_mkspecial(pud_t pud)
> }
> #endif
>
> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> +static inline bool pmd_soft_dirty(pmd_t pmd)
> +{
> + return pte_soft_dirty(pmd_pte(pmd));
> +}
> +
> +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
> +}
> +
> +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
> +}
> +
> +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
> +static inline bool pmd_swp_soft_dirty(pmd_t pmd)
> +{
> + return pte_swp_soft_dirty(pmd_pte(pmd));
> +}
> +
> +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
> +}
> +
> +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
> +}
> +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> +
> static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
> pmd_t *pmdp, pmd_t pmd)
> {
> @@ -1005,7 +1071,8 @@ static inline pud_t pud_modify(pud_t pud, pgprot_t newprot)
> *
> * Format of swap PTE:
> * bit 0: _PAGE_PRESENT (zero)
> - * bit 1 to 3: _PAGE_LEAF (zero)
> + * bit 1 to 2: (zero)
> + * bit 3: _PAGE_SWP_SOFT_DIRTY
> * bit 5: _PAGE_PROT_NONE (zero)
> * bit 6: exclusive marker
> * bits 7 to 11: swap type
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V8 0/3] riscv: mm: Add soft-dirty and uffd-wp support
2025-06-23 23:03 ` Palmer Dabbelt
@ 2025-06-24 13:45 ` Ved Shanbhogue
0 siblings, 0 replies; 8+ messages in thread
From: Ved Shanbhogue @ 2025-06-24 13:45 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: zhangchunyan, Paul Walmsley, aou, Alexandre Ghiti, akpm,
linux-riscv, debug, linux-kernel, zhang.lyra
Palmer wrote:
>>[1] https://github.com/riscv/Svrsw60t59b.git
>
>This 404s (with or without the ".git" suffix). I remember seeing the
>spec at some point, but I can't find it anywhwere else.
The ISA specification is available here:
https://github.com/riscv/riscv-isa-manual/pull/1907
The corresponding IOMMU extension that enumerates support
for Svrsw60t59b is tracked here:
https://github.com/riscv-non-isa/riscv-iommu/pull/543
regards
ved
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2025-06-23 23:19 ` Palmer Dabbelt
2025-06-19 6:52 ` [PATCH V8 3/3] riscv: mm: Add uffd write-protect support Chunyan Zhang
2025-06-19 9:34 ` [PATCH V8 0/3] riscv: mm: Add soft-dirty and uffd-wp support Chunyan Zhang
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