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From: Anup Patel <anup@brainfault.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
	 atishp@atishpatra.org, palmer@dabbelt.com, haibo1.xu@intel.com
Subject: Re: [PATCH v2 1/6] RISC-V: KVM: Don't add SBI multi regs in get-reg-list
Date: Wed, 13 Dec 2023 22:53:51 +0530	[thread overview]
Message-ID: <CAAhSdy0Moex5DnpDUZWTOOKDRbr9GF7NDRCf+x78pLqh=ZLRzg@mail.gmail.com> (raw)
In-Reply-To: <20231213170951.93453-9-ajones@ventanamicro.com>

On Wed, Dec 13, 2023 at 10:39 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> The multi regs are derived from the single registers. Only list the
> single registers in get-reg-list. This also makes the SBI extension
> register listing consistent with the ISA extension register listing.
>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Haibo Xu <haibo1.xu@intel.com>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
>  arch/riscv/kvm/vcpu_onereg.c | 36 ++----------------------------------
>  1 file changed, 2 insertions(+), 34 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index f8c9fa0c03c5..f9bfa8a5db21 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -933,20 +933,12 @@ static inline unsigned long num_isa_ext_regs(const struct kvm_vcpu *vcpu)
>
>  static inline unsigned long num_sbi_ext_regs(void)
>  {
> -       /*
> -        * number of KVM_REG_RISCV_SBI_SINGLE +
> -        * 2 x (number of KVM_REG_RISCV_SBI_MULTI)
> -        */
> -       return KVM_RISCV_SBI_EXT_MAX + 2*(KVM_REG_RISCV_SBI_MULTI_REG_LAST+1);
> +       return KVM_RISCV_SBI_EXT_MAX;
>  }
>
>  static int copy_sbi_ext_reg_indices(u64 __user *uindices)
>  {
> -       int n;
> -
> -       /* copy KVM_REG_RISCV_SBI_SINGLE */
> -       n = KVM_RISCV_SBI_EXT_MAX;
> -       for (int i = 0; i < n; i++) {
> +       for (int i = 0; i < KVM_RISCV_SBI_EXT_MAX; i++) {
>                 u64 size = IS_ENABLED(CONFIG_32BIT) ?
>                            KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
>                 u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_SBI_EXT |
> @@ -959,30 +951,6 @@ static int copy_sbi_ext_reg_indices(u64 __user *uindices)
>                 }
>         }
>
> -       /* copy KVM_REG_RISCV_SBI_MULTI */
> -       n = KVM_REG_RISCV_SBI_MULTI_REG_LAST + 1;
> -       for (int i = 0; i < n; i++) {
> -               u64 size = IS_ENABLED(CONFIG_32BIT) ?
> -                          KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
> -               u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_SBI_EXT |
> -                         KVM_REG_RISCV_SBI_MULTI_EN | i;
> -
> -               if (uindices) {
> -                       if (put_user(reg, uindices))
> -                               return -EFAULT;
> -                       uindices++;
> -               }
> -
> -               reg = KVM_REG_RISCV | size | KVM_REG_RISCV_SBI_EXT |
> -                         KVM_REG_RISCV_SBI_MULTI_DIS | i;
> -
> -               if (uindices) {
> -                       if (put_user(reg, uindices))
> -                               return -EFAULT;
> -                       uindices++;
> -               }
> -       }
> -
>         return num_sbi_ext_regs();
>  }
>
> --
> 2.43.0
>

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  reply	other threads:[~2023-12-13 17:24 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-13 17:09 [PATCH v2 0/6] RISC-V: KVM: Make SBI uapi consistent with ISA uapi Andrew Jones
2023-12-13 17:09 ` [PATCH v2 1/6] RISC-V: KVM: Don't add SBI multi regs in get-reg-list Andrew Jones
2023-12-13 17:23   ` Anup Patel [this message]
2023-12-13 17:09 ` [PATCH v2 2/6] KVM: riscv: selftests: Drop SBI multi registers Andrew Jones
2023-12-13 17:24   ` Anup Patel
2023-12-13 17:09 ` [PATCH v2 3/6] RISC-V: KVM: Make SBI uapi consistent with ISA uapi Andrew Jones
2023-12-13 17:35   ` Anup Patel
2023-12-13 17:09 ` [PATCH v2 4/6] KVM: riscv: selftests: Add RISCV_SBI_EXT_REG Andrew Jones
2023-12-13 17:36   ` Anup Patel
2023-12-13 17:09 ` [PATCH v2 5/6] KVM: riscv: selftests: Use register subtypes Andrew Jones
2023-12-13 17:39   ` Anup Patel
2023-12-13 17:09 ` [PATCH v2 6/6] RISC-V: KVM: selftests: Treat SBI ext regs like ISA ext regs Andrew Jones
2023-12-13 17:42   ` Anup Patel
2023-12-14  5:19 ` [PATCH v2 0/6] RISC-V: KVM: Make SBI uapi consistent with ISA uapi Anup Patel

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