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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=47K6Qgo5QbrZVacaid1WG9JiEbdXdWfBJ5xwgMh492Q=; b=kT07XavIB8+dCirQBeDQH4gOevmpRaWi2vPlavylueSzIEyYtjgizsiSwvjXsxpIfg r8rPeNRlqoD+jaeYZivhcPoTMrGLfkCosyA74lsSSAS95EBkkVRveRh9uAPfPcmmjIVV LSlA8y3JdWMdb1bAoX1WZkGVVlKy+wBn6gY9/hdFWDe1N2uYzl8zGBr8/UXWTSXj+ofr NnjMsHCYnsaRkDxRmvk0xBgiI7pIKAyh4YQrrEyfrSxiXTcMQKOyuEnycye+lS+ZVEbS 8EPO0EaSE/8iccRXiB344sXi1PNgPtv97yTgsYfgeeps+HSM1xQLZR9c0sTh1DCVJbUB Pdjg== X-Gm-Message-State: APjAAAU+WVM11WRwNhioLq3VMQZvOK2tOV/sQeElM31jYHPNjxXBbufW 9RU3HIWbTiczkZJumCYnIA4Uhq/J91GrZnOMrCQ= X-Google-Smtp-Source: APXvYqy9JqFCYGeBYIGRwK0STC3uyqMmE3umCULOglzUZYV5R/oHxsaevcpDD0VVoIXgi5fdeCDD/6ktHdvpucpNCOA= X-Received: by 2002:a1c:cfc5:: with SMTP id f188mr94263067wmg.24.1564464405064; Mon, 29 Jul 2019 22:26:45 -0700 (PDT) MIME-Version: 1.0 References: <20190729115544.17895-1-anup.patel@wdc.com> <72e9f668-f496-3fca-a1a8-a3c3122a3fd9@redhat.com> In-Reply-To: <72e9f668-f496-3fca-a1a8-a3c3122a3fd9@redhat.com> From: Anup Patel Date: Tue, 30 Jul 2019 10:56:33 +0530 Message-ID: Subject: Re: [RFC PATCH 00/16] KVM RISC-V Support To: Paolo Bonzini X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190729_222649_117756_5579E01B X-CRM114-Status: GOOD ( 13.94 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Palmer Dabbelt , Daniel Lezcano , "kvm@vger.kernel.org" , Radim K , Anup Patel , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alistair Francis , Paul Walmsley , Thomas Gleixner , "linux-riscv@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Jul 30, 2019 at 3:17 AM Paolo Bonzini wrote: > > On 29/07/19 13:56, Anup Patel wrote: > > This series adds initial KVM RISC-V support. Currently, we are able to boot > > RISC-V 64bit Linux Guests with multiple VCPUs. > > > > Few key aspects of KVM RISC-V added by this series are: > > 1. Minimal possible KVM world-switch which touches only GPRs and few CSRs. > > 2. Full Guest/VM switch is done via vcpu_get/vcpu_put infrastructure. > > 3. KVM ONE_REG interface for VCPU register access from user-space. > > 4. PLIC emulation is done in user-space. In-kernel PLIC emulation, will > > be added in future. > > 5. Timer and IPI emuation is done in-kernel. > > 6. MMU notifiers supported. > > 7. FP lazy save/restore supported. > > 8. SBI v0.1 emulation for KVM Guest available. > > > > More feature additions and enhancments will follow after this series and > > eventually KVM RISC-V will be at-par with other architectures. > > This looks clean and it shouldn't take long to have it merged. Please > sort out the MAINTAINERS additions. It would also be nice if > tools/testing/selftests/kvm/ worked with RISC-V from the beginning; > there have been recent ARM and s390 ports that you can take some > inspiration from. Thanks Paolo. We will certainly include a patch in v2 series for MAINTAINERS entry. We referred existing implementation of KVM ARM/ARM64, KVM powerpc and KVM mips when we started KVM RISC-V port. Here's a brief TODO list which we want to immediately work upon after this series: 1. Handle trap from unpriv access in SBI v0.1 emulation 2. In-kernel PLIC emulation 3. SBI v0.2 emulation in-kernel 4. SBI v0.2 hart hotplug emulation in-kernel 5. ..... and so on ..... We will include above TODO list in v2 series cover letter as well. Apart from above, we also have a more exhaustive TODO list based on study of other KVM ports which we want to discuss at upcoming LPC 2019. We were thinking to keep KVM RISC-V disabled by default (i.e. keep it experimental) until we have validated it on some FPGA or real HW. For now, users can explicitly enable it and play-around on QEMU emulation. I hope this is fine with most people ? Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv