From: Guo Ren <guoren@kernel.org>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Albert Ou <aou@eecs.berkeley.edu>,
linux-kernel@vger.kernel.org, Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 2/2] riscv: errata: prefix T-Head mnemonics with th.
Date: Sun, 27 Aug 2023 06:18:40 -0400 [thread overview]
Message-ID: <CAJF2gTS1P-1PhWM6qLowbAPm8N0iPyq+88+2=SunCdAY07fe1g@mail.gmail.com> (raw)
In-Reply-To: <20230827090813.1353-3-jszhang@kernel.org>
On Sun, Aug 27, 2023 at 5:20 AM Jisheng Zhang <jszhang@kernel.org> wrote:
>
> From: Icenowy Zheng <uwu@icenowy.me>
>
> T-Head now maintains some specification for their extended instructions
> at [1], in which all instructions are prefixed "th.".
>
> Follow this practice in the kernel comments.
>
> Link: https://github.com/T-head-Semi/thead-extension-spec [1]
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> arch/riscv/include/asm/errata_list.h | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index feab334dd832..98ecab053dd2 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -90,25 +90,25 @@ asm volatile(ALTERNATIVE( \
> #endif
>
> /*
> - * dcache.ipa rs1 (invalidate, physical address)
> + * th.dcache.ipa rs1 (invalidate, physical address)
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000001 01010 rs1 000 00000 0001011
> - * dache.iva rs1 (invalida, virtual address)
> + * th.dache.iva rs1 (invalida, virtual address)
> * 0000001 00110 rs1 000 00000 0001011
> *
> - * dcache.cpa rs1 (clean, physical address)
> + * th.dcache.cpa rs1 (clean, physical address)
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000001 01001 rs1 000 00000 0001011
> - * dcache.cva rs1 (clean, virtual address)
> + * th.dcache.cva rs1 (clean, virtual address)
> * 0000001 00101 rs1 000 00000 0001011
> *
> - * dcache.cipa rs1 (clean then invalidate, physical address)
> + * th.dcache.cipa rs1 (clean then invalidate, physical address)
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000001 01011 rs1 000 00000 0001011
> - * dcache.civa rs1 (... virtual address)
> + * th.dcache.civa rs1 (... virtual address)
> * 0000001 00111 rs1 000 00000 0001011
> *
> - * sync.s (make sure all cache operations finished)
> + * th.sync.s (make sure all cache operations finished)
Reviewed-by: Guo Ren <guoren@kernel.org>
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000000 11001 00000 000 00000 0001011
> */
> --
> 2.40.1
>
--
Best Regards
Guo Ren
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next prev parent reply other threads:[~2023-08-27 10:19 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-27 9:08 [PATCH v2 0/2] riscv: errata: improve T-Head CMO Jisheng Zhang
2023-08-27 9:08 ` [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding Jisheng Zhang
2023-09-04 19:43 ` Drew Fustini
2023-09-04 19:59 ` Drew Fustini
2023-08-27 9:08 ` [PATCH v2 2/2] riscv: errata: prefix T-Head mnemonics with th Jisheng Zhang
2023-08-27 10:18 ` Guo Ren [this message]
2023-08-27 11:21 ` [PATCH v2 0/2] riscv: errata: improve T-Head CMO Jisheng Zhang
2023-09-13 0:37 ` patchwork-bot+linux-riscv
2023-11-02 20:20 ` patchwork-bot+linux-riscv
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