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Tue, 18 Oct 2022 19:55:23 -0700 (PDT) X-Gm-Message-State: ACrzQf2XxsZL1ZhcMUaNvtaxRa83PxfIlIsnOqDWp0lNiD8v2XU99WDm Fj+w7/lLIXhERCPYcYbok6ljzxAjxQ8OtJ6APyQ= X-Google-Smtp-Source: AMsMyM5C2i3Ly90Zfv1TFQiVbzhvl/qqipUlQgQ5lvq37RcRpl/8aSWNrQoateRH2fQeJuj+TJ+GtxnpltGYrkmr3Ko= X-Received: by 2002:a9d:60dd:0:b0:661:b6ae:aa7a with SMTP id b29-20020a9d60dd000000b00661b6aeaa7amr2779172otk.140.1666148122239; Tue, 18 Oct 2022 19:55:22 -0700 (PDT) MIME-Version: 1.0 References: <20220928162007.3791-1-jszhang@kernel.org> <20220928162007.3791-5-jszhang@kernel.org> In-Reply-To: From: Guo Ren Date: Wed, 19 Oct 2022 10:55:09 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 4/4] riscv: entry: consolidate general regs saving into save_gp To: Jisheng Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Nathan Chancellor , Nick Desaulniers , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221018_195526_284690_6C3D7CFE X-CRM114-Status: GOOD ( 20.04 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Sep 30, 2022 at 12:11 AM Jisheng Zhang wrote: > > On Thu, Sep 29, 2022 at 11:59:00AM +0800, Guo Ren wrote: > > On Thu, Sep 29, 2022 at 12:29 AM Jisheng Zhang wrote: > > > > > > Consolidate the saving/restoring GPs(except ra, sp and tp) into > > > save_gp/restore_gp macro. > > > > > > No functional change intended. > > > > > > Signed-off-by: Jisheng Zhang > > > --- > > > arch/riscv/include/asm/asm.h | 65 +++++++++++++++++++++++++ > > > arch/riscv/kernel/entry.S | 87 ++-------------------------------- > > > arch/riscv/kernel/mcount-dyn.S | 58 +---------------------- > > > 3 files changed, 70 insertions(+), 140 deletions(-) > > > > > > diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h > > > index 1b471ff73178..2f3b49536e9d 100644 > > > --- a/arch/riscv/include/asm/asm.h > > > +++ b/arch/riscv/include/asm/asm.h > > > @@ -68,6 +68,7 @@ > > > #endif > > > > > > #ifdef __ASSEMBLY__ > > > +#include > > > > > > /* Common assembly source macros */ > > > > > > @@ -80,6 +81,70 @@ > > > .endr > > > .endm > > > > > > + /* save all GPs except ra, sp and tp */ > > > + .macro save_gp > > How about leave x3(gp) out of the macro, and define: > > .marco save_from_x5_to_x31 > > .marco restore_from_x5_to_x31 > > Good idea, will do in next version. Where is the next version? I want to involve the patch in my generic entry series, it would help in the coding convention of the entry code. > > Thanks -- Best Regards Guo Ren _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv