* [PATCH] dt-bindings: riscv: Add SiFive vendor extensions description
@ 2025-07-08 6:52 Nick Hu
2025-07-09 16:00 ` Conor Dooley
0 siblings, 1 reply; 3+ messages in thread
From: Nick Hu @ 2025-07-08 6:52 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv,
devicetree, linux-kernel
Cc: Nick Hu, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Albert Ou
Add description for SiFive vendor extensions "xsfcflushdlone",
"xsfpgflushdlone" and "xsfcease".
Signed-off-by: Nick Hu <nick.hu@sifive.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 72c1b063fdfe..10c37c61243d 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -626,6 +626,24 @@ properties:
https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
# SiFive
+ - const: xsfcease
+ description:
+ SiFive CEASE Instruction Extensions Specification.
+ See more details in
+ https://www.sifive.com/document-file/freedom-u740-c000-manual
+
+ - const: xsfcflushdlone
+ description:
+ SiFive L1D Cache Flush Instruction Extensions Specification.
+ See more details in
+ https://www.sifive.com/document-file/freedom-u740-c000-manual
+
+ - const: xsfpgflushdlone
+ description:
+ SiFive PGFLUSH Instruction Extensions for the power management. The
+ CPU will flush the L1D and enter the cease state after executing
+ the instruction.
+
- const: xsfqmaccdod
description:
SiFive Int8 Matrix Multiplication Extensions Specification.
--
2.17.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] dt-bindings: riscv: Add SiFive vendor extensions description
2025-07-08 6:52 [PATCH] dt-bindings: riscv: Add SiFive vendor extensions description Nick Hu
@ 2025-07-09 16:00 ` Conor Dooley
2025-07-10 4:57 ` Nick Hu
0 siblings, 1 reply; 3+ messages in thread
From: Conor Dooley @ 2025-07-09 16:00 UTC (permalink / raw)
To: Nick Hu
Cc: Paul Walmsley, Palmer Dabbelt, linux-riscv, devicetree,
linux-kernel, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Albert Ou
[-- Attachment #1.1: Type: text/plain, Size: 1870 bytes --]
On Tue, Jul 08, 2025 at 02:52:42PM +0800, Nick Hu wrote:
> Add description for SiFive vendor extensions "xsfcflushdlone",
> "xsfpgflushdlone" and "xsfcease".
>
> Signed-off-by: Nick Hu <nick.hu@sifive.com>
You have this, but no user or anything along with it. What's actually
making use of this? If it's just for the SBI impl or w/e then say that.
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 72c1b063fdfe..10c37c61243d 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -626,6 +626,24 @@ properties:
> https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
>
> # SiFive
> + - const: xsfcease
> + description:
> + SiFive CEASE Instruction Extensions Specification.
> + See more details in
> + https://www.sifive.com/document-file/freedom-u740-c000-manual
> +
> + - const: xsfcflushdlone
> + description:
> + SiFive L1D Cache Flush Instruction Extensions Specification.
> + See more details in
> + https://www.sifive.com/document-file/freedom-u740-c000-manual
> +
> + - const: xsfpgflushdlone
> + description:
> + SiFive PGFLUSH Instruction Extensions for the power management. The
> + CPU will flush the L1D and enter the cease state after executing
> + the instruction.
> +
> - const: xsfqmaccdod
> description:
> SiFive Int8 Matrix Multiplication Extensions Specification.
> --
> 2.17.1
>
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] dt-bindings: riscv: Add SiFive vendor extensions description
2025-07-09 16:00 ` Conor Dooley
@ 2025-07-10 4:57 ` Nick Hu
0 siblings, 0 replies; 3+ messages in thread
From: Nick Hu @ 2025-07-10 4:57 UTC (permalink / raw)
To: Conor Dooley
Cc: Paul Walmsley, Palmer Dabbelt, linux-riscv, devicetree,
linux-kernel, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Albert Ou
On Thu, Jul 10, 2025 at 12:00 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, Jul 08, 2025 at 02:52:42PM +0800, Nick Hu wrote:
> > Add description for SiFive vendor extensions "xsfcflushdlone",
> > "xsfpgflushdlone" and "xsfcease".
> >
> > Signed-off-by: Nick Hu <nick.hu@sifive.com>
>
> You have this, but no user or anything along with it. What's actually
> making use of this? If it's just for the SBI impl or w/e then say that.
>
It's for the SBI implementation. I'll update it in the commit message.
Thanks!
Best Regard,
Nick
> > ---
> > .../devicetree/bindings/riscv/extensions.yaml | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index 72c1b063fdfe..10c37c61243d 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -626,6 +626,24 @@ properties:
> > https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
> >
> > # SiFive
> > + - const: xsfcease
> > + description:
> > + SiFive CEASE Instruction Extensions Specification.
> > + See more details in
> > + https://www.sifive.com/document-file/freedom-u740-c000-manual
> > +
> > + - const: xsfcflushdlone
> > + description:
> > + SiFive L1D Cache Flush Instruction Extensions Specification.
> > + See more details in
> > + https://www.sifive.com/document-file/freedom-u740-c000-manual
> > +
> > + - const: xsfpgflushdlone
> > + description:
> > + SiFive PGFLUSH Instruction Extensions for the power management. The
> > + CPU will flush the L1D and enter the cease state after executing
> > + the instruction.
> > +
> > - const: xsfqmaccdod
> > description:
> > SiFive Int8 Matrix Multiplication Extensions Specification.
> > --
> > 2.17.1
> >
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2025-07-08 6:52 [PATCH] dt-bindings: riscv: Add SiFive vendor extensions description Nick Hu
2025-07-09 16:00 ` Conor Dooley
2025-07-10 4:57 ` Nick Hu
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