* [PATCH 02/17] riscv: Extending cpufeature.c to detect V-extension
@ 2022-09-21 16:46 Chris Stillson
0 siblings, 0 replies; 4+ messages in thread
From: Chris Stillson @ 2022-09-21 16:46 UTC (permalink / raw)
To: linux-riscv; +Cc: palmer
Current cpufeature.c doesn't support detecting V-extension, because
"rv64" also contain a 'v' letter and we need to skip it.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
---
arch/riscv/include/uapi/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/hwcap.h
b/arch/riscv/include/uapi/asm/hwcap.h
index 46dc3f5ee99f..c52bb7bbbabe 100644
--- a/arch/riscv/include/uapi/asm/hwcap.h
+++ b/arch/riscv/include/uapi/asm/hwcap.h
@@ -21,5 +21,6 @@
#define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A'))
#define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A'))
#define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A'))
+#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A'))
#endif /* _UAPI_ASM_RISCV_HWCAP_H */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 553d755483ed..8d4448c2d4f4 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -83,6 +83,7 @@ void __init riscv_fill_hwcap(void)
isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
+ isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V;
elf_hwcap = 0;
--
2.25.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 00/17] Prctl to enable vector commands, previous vector patches rebased
@ 2022-09-21 19:46 Chris Stillson
2022-09-21 19:46 ` [PATCH 02/17] riscv: Extending cpufeature.c to detect V-extension Chris Stillson
0 siblings, 1 reply; 4+ messages in thread
From: Chris Stillson @ 2022-09-21 19:46 UTC (permalink / raw)
To: linux-riscv, jpalmer, kvm-riscv; +Cc: Chris Stillson
This patch adds a prctl to enable, disable, or query whether vectors are enabled or not. This is to allow a process to "opt out" of the overhead incurred by using vectors. Because this is build on top of an existing set of patches to work with vectors, they have been rebased to Linux 6.0-rc1.
Chris Stillson (1):
riscv: prctl to enable vector commands
Greentime Hu (9):
riscv: Add new csr defines related to vector extension
riscv: Add has_vector/riscv_vsize to save vector features.
riscv: Add vector struct and assembler definitions
riscv: Add task switch support for vector
riscv: Add ptrace vector support
riscv: Add sigcontext save/restore for vector
riscv: Add support for kernel mode vector
riscv: Add vector extension XOR implementation
riscv: Fix a kernel panic issue if $s2 is set to a specific value
before entering Linux
Guo Ren (4):
riscv: Rename __switch_to_aux -> fpu
riscv: Extending cpufeature.c to detect V-extension
riscv: Add vector feature to compile
riscv: Reset vector register
Vincent Chen (3):
riscv: signal: Report signal frame size to userspace via auxv
riscv: Add V extension to KVM ISA allow list
riscv: KVM: Add vector lazy save/restore support
arch/riscv/Kconfig | 15 +-
arch/riscv/Makefile | 1 +
arch/riscv/configs/defconfig | 6 +
arch/riscv/include/asm/csr.h | 16 ++-
arch/riscv/include/asm/elf.h | 47 +++---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/kvm_host.h | 2 +
arch/riscv/include/asm/kvm_vcpu_vector.h | 65 +++++++++
arch/riscv/include/asm/processor.h | 9 ++
arch/riscv/include/asm/switch_to.h | 83 ++++++++++-
arch/riscv/include/asm/vector.h | 17 +++
arch/riscv/include/asm/xor.h | 82 +++++++++++
arch/riscv/include/uapi/asm/auxvec.h | 1 +
arch/riscv/include/uapi/asm/hwcap.h | 1 +
arch/riscv/include/uapi/asm/kvm.h | 7 +
arch/riscv/include/uapi/asm/ptrace.h | 23 +++
arch/riscv/include/uapi/asm/sigcontext.h | 24 ++++
arch/riscv/kernel/Makefile | 2 +
arch/riscv/kernel/asm-offsets.c | 15 ++
arch/riscv/kernel/cpufeature.c | 21 +++
arch/riscv/kernel/entry.S | 6 +-
arch/riscv/kernel/head.S | 37 ++++-
arch/riscv/kernel/kernel_mode_vector.c | 132 +++++++++++++++++
arch/riscv/kernel/process.c | 61 ++++++++
arch/riscv/kernel/ptrace.c | 71 ++++++++++
arch/riscv/kernel/riscv_ksyms.c | 6 +
arch/riscv/kernel/signal.c | 173 ++++++++++++++++++++++-
arch/riscv/kernel/vector.S | 102 +++++++++++++
arch/riscv/kvm/Makefile | 1 +
arch/riscv/kvm/vcpu.c | 32 +++++
arch/riscv/kvm/vcpu_switch.S | 69 +++++++++
arch/riscv/kvm/vcpu_vector.c | 173 +++++++++++++++++++++++
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/xor.S | 81 +++++++++++
include/uapi/linux/elf.h | 1 +
include/uapi/linux/prctl.h | 6 +
kernel/sys.c | 7 +
37 files changed, 1355 insertions(+), 42 deletions(-)
create mode 100644 arch/riscv/include/asm/kvm_vcpu_vector.h
create mode 100644 arch/riscv/include/asm/vector.h
create mode 100644 arch/riscv/include/asm/xor.h
create mode 100644 arch/riscv/kernel/kernel_mode_vector.c
create mode 100644 arch/riscv/kernel/vector.S
create mode 100644 arch/riscv/kvm/vcpu_vector.c
create mode 100644 arch/riscv/lib/xor.S
--
2.25.1
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^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH 02/17] riscv: Extending cpufeature.c to detect V-extension
2022-09-21 19:46 [PATCH 00/17] Prctl to enable vector commands, previous vector patches rebased Chris Stillson
@ 2022-09-21 19:46 ` Chris Stillson
2022-09-21 20:11 ` Conor Dooley
0 siblings, 1 reply; 4+ messages in thread
From: Chris Stillson @ 2022-09-21 19:46 UTC (permalink / raw)
To: linux-riscv, jpalmer, kvm-riscv
Cc: Guo Ren, Guo Ren, Anup Patel, Greentime Hu, Palmer Dabbelt
From: Guo Ren <ren_guo@c-sky.com>
Current cpufeature.c doesn't support detecting V-extension, because
"rv64" also contain a 'v' letter and we need to skip it.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
---
arch/riscv/include/uapi/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h
index 46dc3f5ee99f..c52bb7bbbabe 100644
--- a/arch/riscv/include/uapi/asm/hwcap.h
+++ b/arch/riscv/include/uapi/asm/hwcap.h
@@ -21,5 +21,6 @@
#define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A'))
#define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A'))
#define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A'))
+#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A'))
#endif /* _UAPI_ASM_RISCV_HWCAP_H */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 553d755483ed..8d4448c2d4f4 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -83,6 +83,7 @@ void __init riscv_fill_hwcap(void)
isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
+ isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V;
elf_hwcap = 0;
--
2.25.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH 02/17] riscv: Extending cpufeature.c to detect V-extension
2022-09-21 19:46 ` [PATCH 02/17] riscv: Extending cpufeature.c to detect V-extension Chris Stillson
@ 2022-09-21 20:11 ` Conor Dooley
2022-09-21 21:33 ` Conor Dooley
0 siblings, 1 reply; 4+ messages in thread
From: Conor Dooley @ 2022-09-21 20:11 UTC (permalink / raw)
To: Chris Stillson
Cc: linux-riscv, palmer, kvm-riscv, Guo Ren, Guo Ren, Anup Patel,
Greentime Hu, Palmer Dabbelt
On Wed, Sep 21, 2022 at 12:46:14PM -0700, Chris Stillson wrote:
Hey Chris,
Looks like this only partially made it to the list. The cover letter is
missing as are a bunch of the patches in the middle, see:
https://lore.kernel.org/linux-riscv/20220921194629.1480202-3-stillson@rivosinc.com/T/#t
Also, when you run format-patch to generate the patches, please add the
`-v` flag with a number so that the patchset gets the version number
added to it.
Ohh, and Palmer's non-rivos email looks wrong?
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 02/17] riscv: Extending cpufeature.c to detect V-extension
2022-09-21 20:11 ` Conor Dooley
@ 2022-09-21 21:33 ` Conor Dooley
0 siblings, 0 replies; 4+ messages in thread
From: Conor Dooley @ 2022-09-21 21:33 UTC (permalink / raw)
To: Chris Stillson
Cc: linux-riscv, palmer, kvm-riscv, Guo Ren, Guo Ren, Anup Patel,
Greentime Hu, Palmer Dabbelt
On Wed, Sep 21, 2022 at 09:11:56PM +0100, Conor Dooley wrote:
> On Wed, Sep 21, 2022 at 12:46:14PM -0700, Chris Stillson wrote:
>
> Hey Chris,
>
> Looks like this only partially made it to the list. The cover letter is
> missing as are a bunch of the patches in the middle, see:
> https://lore.kernel.org/linux-riscv/20220921194629.1480202-3-stillson@rivosinc.com/T/#t
nvm, rest of it seems to have finally made it through now.
> Also, when you run format-patch to generate the patches, please add the
> `-v` flag with a number so that the patchset gets the version number
> added to it.
>
> Ohh, and Palmer's non-rivos email looks wrong?
Rest still applies though & rerolling as v12 would be nice so that the
tools don't get confused about which version is which since you've now
sent a pair of v1s.
Your SoB is still missing from the individual patches too.
Getting there though, this one is at least threaded & the patches are
not whitespace damaged/line wrapped anymore AFAICT.
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2022-09-21 19:46 ` [PATCH 02/17] riscv: Extending cpufeature.c to detect V-extension Chris Stillson
2022-09-21 20:11 ` Conor Dooley
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